On Sun, 2012-02-05 at 18:25 +0330, ali hagigat wrote:
My motherboard is: Pentium III, 82815, ICH2.
I configured coreboot for Intel, d810e2cb motherboard. The coreboot stops printing the following lines on the serial port:
coreboot-4.0-1959-g950f20a-dirty Sun Feb 5 17:52:27 IRST 2012 starting... SMBus controller enabled No DIMM found in slot 0 No DIMM found in slot 1 DRP calculated to 0x00 BUFF_SC calculated to 0x0000 Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image.
Where is the problem. I just replaced sdram_enable() with a routine which I am sure that it initializes RAM correctly. The rest is the pure Coreboot code.
Hi
Enable most verbose logging (8 ?) and post new logs. Also readers on the list have currently no clue how You obtained and modified your local copy of Coreboot.
Your posted serial log appears exactly as from the coreboot sources. Double-check you have really changed the call to sdram_enable(), recompiled, flashed correctly etc.
If you are running closed-source assembly code copy-pasted and mixed within coreboot, don't expect much assistance until you have convinced us that at the minimum ram_check() passes without errors after sdram_enable() :)
The following patch contains a replacement ram_check() that I consider more reliable or thorough: http://review.coreboot.org/294
Thanks, KM