On Tue, Jun 07, 2016 at 09:40:59AM +0200, maxime de Roucy wrote:
Le 7 juin 2016 2:09 AM, "Piotr Król" piotr.krol@3mdeb.com a écrit :
Hi Maxime,
I'm working on support for PC Engines APU2 (AMD GX-412TC) board and I finally manage to boot Voyage Linux and run memtest86+. There some limitations and concerns that I have and hope you can advise how to proceed.
I wrote a blog article about coreboot on apu1d. Maybe some informations can help you with apu2. https://pelican.craoc.fr/coreboot.html
Thanks I will take a look at it.
- APU2 got only UART interface and to make it accept input character I
had to port some changes from out of tree SeaBIOS. I managed to merge it with upstream version and it seems to work for APU2. Some of those changes are very specific to APU2. Code is here: https://github.com/pcengines/seabios/commits/apu2-support
It seams the SeaBIOS prefer to use/promote sgabios instead of building it's own serial input solution.
http://www.seabios.org/pipermail/seabios/2016-May/010677.html
I personaly also prefer sgabios as it allow the user to chainload non serial aware solution. See note about sgabios in this section : https://pelican.craoc.fr/coreboot.html#seabios_1
End users seems to have problems with sgabios and that's why I was asked to remove sgabios support. It looks like using Google sgabios is design decision, so I will gather information about bugs/features they faced and then see what can be done to fix that.
Where I should push patches for sgabios, if any ?
- I also had to modify memtest86plus because it hanged on code looking
for SPD. This platform do not use memory modules, just chips soldered on board. At this point there is SPD_DISABLE define that disable SPD reading. I'm not sure if this is correct approach and if this should be pushed for review before proving it work ? https://github.com/pcengines/memtest86plus/commits/apu2
Did you use the coreboot memtest86plus repo ? https://review.coreboot.org/gitweb/cgit/memtest86plus.git/
Yes I did.