Author: hailfinger Date: 2009-09-22 12:03:15 +0200 (Tue, 22 Sep 2009) New Revision: 4648
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb Log: r4534 introduced devicetree.cb in every mainboard directory, but didn't copy any comment lines before the start of the device tree. Fix up amd/pistachio and technexion/tim8960.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Peter Stuge peter@stuge.se
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb 2009-09-22 09:43:25 UTC (rev 4647) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb 2009-09-22 10:03:15 UTC (rev 4648) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_AM2
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb 2009-09-22 09:43:25 UTC (rev 4647) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb 2009-09-22 10:03:15 UTC (rev 4648) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff80000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_S1G1