On 17.03.2009 00:24, Peter Stuge wrote:
Carl-Daniel Hailfinger wrote:
Can't we just rely on the SPI/LPC selection register to be unchanged after boot?
That would be perfect.
This hunk does it, it even explains what is being done.
--- chipset_enable.c (revision 312) +++ chipset_enable.c (working copy) @@ -680,8 +680,16 @@ flashbus = BUS_TYPE_SB600_SPI;
/* Enable SPI ROM in SB600 PM register. */ + /* If we enable SPI ROM here, we have to disable it after we leave. + * But how can we know which ROM we are going to handle? So we have + * to trade off. We only access LPC ROM if we boot via LPC ROM. And + * only SPI ROM if we boot via SPI ROM. If you want to do it crossly, + * you have to use the code below. + */ + /* OUTB(0x8f, 0xcd6); OUTB(0x0e, 0xcd7); + */
return 0; }
If someone deliberately changes that register,
Which register? I couldn't find one. :\
See the patch hunk above. Look for CD6 in the SB600 RRG. Notice CD6 is PM_INDEX. CD7 is PM_DATA. Look at section 2.3.3.2 Power Management (PM) Registers. 8F is FakeAsrEn. FakeAsrEn has two interesting fields: UseBypassRom and BypassRomSel.
Basically, the patch hunk above does simply remove the forcing of SPI access and relies on the default boot-up method. Back when you NAKed that change, I wondered why but I assumed you wanted some more design to go into it.
Other parts of the patch introduce timeout handling to the SB600 SPI functions and change the programming interface a bit.
I think the patch is committable, but it should be split into multiple pieces with one conceptual change each.
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel