Carl-Daniel Hailfinger wrote:
On 28.10.2008 00:40, ron minnich wrote:
On Mon, Oct 27, 2008 at 4:25 PM, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006@gmx.net wrote:
The explanations by Tom and Marc made a few things clear for me:
- The physical HT structure is not what we want to model.
- The appearance of HT and topology in PCI config space is what matters.
- 18.0 is not a PCI bridge, don't pretend it is one
With that in mind, I'd like to propose another dts.
I know that it has its own quirks, but it can serve as a discussion point.
I'm beginning to feel like we're thinking too much.
We were trying to coax physical connections into the dts, but then we
had to ignore them in the code because the logical connections and their
placements were different.
This is the right track. Addressing is what is important for resource
allocation. Later we can add a physical connection for ht that can be
auto-generated runtime if we decide we want to know that as well.
The fact is that whether or not the three HT links are a bridge, there
is routing in there that makes each link logically the parent of a
different set of devices. do we call that a bridge?
Do we ever walk the HT links explicitly in the code?
Not in device code. All that is done in Stage1 early init.
I don't know what to do with bus@1.
I fully agree. That's the weakest point of my dts. We can place all
those devices at bus 1, but for legacy reasons we may want to have them
at bus 0. Our choice.
With the assumption that bus@X should be any number found that matches
the device. Maybe remove the @X. I don't think it does anything. I think
that this is more correct:
bus{
pci@6,0 {
/config/("southbridge/amd/amd8111/pci.dts");
bus{
pci@0,0{
/config/("southbridge/amd/amd8111/usb.dts");
Does the bus indicate anything? Would this work?
pci@6,0 {
/config/("southbridge/amd/amd8111/pci.dts");
pci@0,0{
/config/("southbridge/amd/amd8111/usb.dts");
ah well it's been a long day, will look at this later. For now let's
get myles patch in and try to see where that goes. I think I'm not
ready for this dts. But if myles wants to try it that's fine too.
Sure, as long as the dts is not set in stone, I retract my NACK and
encourage Myles to commit.
This isn't even set in jello, never mind stone! :)
Attached lspci from Serengeti (FAM10 CPU but buses should be the same).
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones@amd.com
http://www.amd.com/embeddedprocessors
00:06.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8111 PCI [1022:7460] (rev 07)
00:07.0 ISA bridge [0601]: Advanced Micro Devices [AMD] AMD-8111 LPC [1022:7468] (rev 05)
00:07.1 IDE interface [0101]: Advanced Micro Devices [AMD] AMD-8111 IDE [1022:7469] (rev 03)
00:07.2 SMBus [0c05]: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 [1022:746a] (rev 02)
00:07.3 Bridge [0680]: Advanced Micro Devices [AMD] AMD-8111 ACPI [1022:746b] (rev 05)
00:0a.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8132 PCI-X Bridge [1022:7458] (rev 11)
00:0a.1 PIC [0800]: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC [1022:7459] (rev 11)
00:0b.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8132 PCI-X Bridge [1022:7458] (rev 11)
00:0b.1 PIC [0800]: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC [1022:7459] (rev 11)
00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200]
00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201]
00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202]
00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203]
00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204]
00:19.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200]
00:19.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201]
00:19.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202]
00:19.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203]
00:19.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204]
01:00.0 USB Controller [0c03]: Advanced Micro Devices [AMD] AMD-8111 USB [1022:7464] (rev 0b)
01:00.1 USB Controller [0c03]: Advanced Micro Devices [AMD] AMD-8111 USB [1022:7464] (rev 0b)
01:04.0 Ethernet controller [0200]: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller [100b:0020]
08:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] AMD-8151 System Controller [1022:7454] (rev 14)
08:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8151 AGP Bridge [1022:7455] (rev 14)
09:00.0 VGA compatible controller [0300]: ATI Technologies Inc RV280 [Radeon 9200] [1002:5961] (rev 01)
09:00.1 Display controller [0380]: ATI Technologies Inc RV280 [Radeon 9200] (Secondary) [1002:5941] (rev 01)
-+-[0000:08]-+-01.0
| -02.0-[0000:09]--+-00.0
| -00.1
-[0000:00]-+-06.0-[0000:01]--+-00.0
| +-00.1
| -04.0
+-07.0
+-07.1
+-07.2
+-07.3
+-0a.0-[0000:02]--
+-0a.1
+-0b.0-[0000:03]--
+-0b.1
+-18.0
+-18.1
+-18.2
+-18.3
+-18.4
+-19.0
+-19.1
+-19.2
+-19.3
-19.4