On 01.03.2008 16:50, Peter Stuge wrote:
On Sat, Mar 01, 2008 at 08:04:54AM -0500, joe@smittys.pointclark.net wrote:
Little confused about SMM? In the nothbridge datasheet it talks about SMM (System Management Space), I do not have any of these registers set, just defaults. In the southbridge datasheet it talks about SMM (special mask mode), I do not have any of these registers set eithor, just defaults. Are these related, or two different things? Do I need to set these registers up?
They are different things.
SMM when talking about flashing refers to System Management Mode which is a special task context supported by mobile-only x86 since mobile 386SL and later also non-mobile x86.
http://en.wikipedia.org/wiki/System_Management_Mode
SMM is entered by triggering an SMI (System Management Interrupt) which can be done either by electrical signal to a dedicated pin on the CPU, or by software traps that are defined when initializing SMM.
Software traps can be set on IO and memory access.
This is the technology used by VSA to emulate legacy hardware on Geodes.
When it comes to flashing, accessing the flash chip as usual causes a software trap and the code in SMM (put in place by the factory BIOS during boot) will determine whether to allow this particular access to continue onto real hardware or just fail and return 0xff.
There have been some stories on the list about what the SMM code does to make it's decision, checksums in reserved memory area and whatnot.
That's why I want to know if this also happens under coreboot. If so, we can rule out that sort of SMM because coreboot does not use SMM yet.
Regards, Carl-Daniel