[coreboot] i945: raminit.c

[Urbez Santana Roma]

in file:
coreboot-v2/src/northbridge/intel/i945/raminit.c

in the function:

static int sdram_capabilities_dual_channel(void)
{
        u32 reg32;

reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
        reg32 >>= 24;
        reg32 &= 1;

return (!reg32);
}

The pci_read_config8 must be pci_read_config32 to read 
the bit 56 of CAPID0? .

Another question.
If the chipset FSB supports 667MHz and chipset only supports DDR2-533
if one DDR2 667MHz or 800Mhz are connected, then FSB
can one set FSB to maximum 667?