[coreboot] [commit] r5818 - trunk/src/include/cpu/x86

[repository service]

Author: mjones
Date: Fri Sep 17 23:38:40 2010
New Revision: 5818
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5818

Log:
AMD Fam10 code breaks with gcc 4.5.0.
Root cause: After function STOP_CAR_AND_CPU disables cache as
ram, the cache as ram stack can no longer be used. Called
functions must be inlined to avoid stack usage. Also, the
compiler must keep local variables register based and not
allocated them from the stack. With gcc 4.5.0, some functions
declared as inline are not being inlined. This patch forces
these functions to always be inlined by adding the qualifier
__attribute__((always_inline)) to their declaration.

Signed-off-by: Scott Duplichan 
Acked-by: Stefan Reinauer 
Acked-by: Marc Jones

Modified:
   trunk/src/include/cpu/x86/cache.h
   trunk/src/include/cpu/x86/msr.h

Modified: trunk/src/include/cpu/x86/cache.h
==============================================================================
--- trunk/src/include/cpu/x86/cache.h	Fri Sep 17 02:13:52 2010	(r5817)
+++ trunk/src/include/cpu/x86/cache.h	Fri Sep 17 23:38:40 2010	(r5818)
@@ -74,7 +74,17 @@
    asm volatile("invd" ::: "memory");
 }

-static inline void enable_cache(void)
+/* The following functions require the always_inline due to AMD
+ * function STOP_CAR_AND_CPU that disables cache as
+ * ram, the cache as ram stack can no longer be used. Called
+ * functions must be inlined to avoid stack usage. Also, the
+ * compiler must keep local variables register based and not
+ * allocated them from the stack. With gcc 4.5.0, some functions
+ * declared as inline are not being inlined. This patch forces
+ * these functions to always be inlined by adding the qualifier
+ * __attribute__((always_inline)) to their declaration.
+ */
+static inline __attribute__((always_inline)) void enable_cache(void)
 {
    unsigned long cr0;
    cr0 = read_cr0();
@@ -82,7 +92,7 @@
    write_cr0(cr0);
 }

-static inline void disable_cache(void)
+static inline __attribute__((always_inline)) void disable_cache(void)
 {
    /* Disable and write back the cache */
    unsigned long cr0;

Modified: trunk/src/include/cpu/x86/msr.h
==============================================================================
--- trunk/src/include/cpu/x86/msr.h	Fri Sep 17 02:13:52 2010	(r5817)
+++ trunk/src/include/cpu/x86/msr.h	Fri Sep 17 23:38:40 2010	(r5818)
@@ -29,7 +29,17 @@
         msr_t msr;
 } msrinit_t;

-static inline msr_t rdmsr(unsigned index)
+/* The following functions require the always_inline due to AMD
+ * function STOP_CAR_AND_CPU that disables cache as
+ * ram, the cache as ram stack can no longer be used. Called
+ * functions must be inlined to avoid stack usage. Also, the
+ * compiler must keep local variables register based and not
+ * allocated them from the stack. With gcc 4.5.0, some functions
+ * declared as inline are not being inlined. This patch forces
+ * these functions to always be inlined by adding the qualifier
+ * __attribute__((always_inline)) to their declaration.
+ */
+static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
 {
    msr_t result;
    __asm__ __volatile__ (
@@ -40,7 +50,7 @@
    return result;
 }

-static inline void wrmsr(unsigned index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
 {
    __asm__ __volatile__ (
    	"wrmsr"