Author: myles Date: Tue Jul 6 22:36:36 2010 New Revision: 5652 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5652
Log: A bug fix: Fix the ctrl_devport_conf_clear to clear the enable bit.
A simplification: Dynamically enable ck804s that are found instead of relying on #defines. Removing an Opteron changes the number of ck804s that are present.
Simple changes to make it easier to compare the factory BIOS with Coreboot when using SerialICE for boards with the Nvidia ck804 chipset: If the mask is zero, don't read the value, just write the new value over it.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Myles Watson mylesgw@gmail.com
Modified: trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -45,7 +45,6 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
/* Used by ck804_early_setup(). */ -#define CK804_NUM 1 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1
Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -79,7 +79,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define CK804_NUM 2 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1
Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/tyan/s2892/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -60,7 +60,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define CK804_NUM 1 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \
Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -73,7 +73,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define CK804_NUM 2 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1
@@ -90,7 +89,6 @@
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
- #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Tue Jul 6 22:36:36 2010 (r5652) @@ -15,7 +15,8 @@ #endif dev = (register_values[i] & ~0xfff) + offset_pci_dev; where = register_values[i] & 0xfff; - reg = pci_read_config32(dev, where); + if (register_values[i+1]) + reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2] + offset_io_base; pci_write_config32(dev, where, reg); @@ -60,7 +61,8 @@ unsigned long reg; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); + if (register_values[i+2]) + reg = pci_read_config32(dev, where); reg &= register_values[i+2]; reg |= register_values[i+3]; pci_write_config32(dev, where, reg); @@ -71,7 +73,8 @@ unsigned where; unsigned reg; where = register_values[i+1] + offset_io_base; - reg = inb(where); + if (register_values[i+2]) + reg = inb(where); reg &= register_values[i+2]; reg |= register_values[i+3]; outb(reg, where); @@ -82,7 +85,8 @@ unsigned where; unsigned long reg; where = register_values[i+1] + offset_io_base; - reg = inl(where); + if (register_values[i+2]) + reg = inl(where); reg &= register_values[i+2]; reg |= register_values[i+3]; outl(reg, where);
Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Jul 6 22:36:36 2010 (r5652) @@ -102,8 +102,8 @@ unsigned *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, + PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, };
int j; @@ -211,9 +211,10 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif
-#if CK804_NUM > 1 + }; + + static const unsigned int ctrl_conf_multiple[] = { RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), -#endif };
static const unsigned int ctrl_conf_slave[] = { @@ -284,7 +285,12 @@ if (busn[j] == 0) { setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master), - PCI_DEV(busn[0], CK804_DEVN_BASE, 0), io_base[0]); + PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]); + if (ck804_num > 1) + setup_resource_map_x_offset(ctrl_conf_multiple, + ARRAY_SIZE(ctrl_conf_multiple), + PCI_DEV(0, CK804_DEVN_BASE, 0), 0); + continue; }