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Hello all,
Here comes some updated patch:
Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the D1F0 bridge without activated I/O and MEM resources, otherwise it will hang whole PCI bus.
U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why does we not.
Second small change just changes a bit which controls the PSTATECTL logic.
Third change deals with the integrated VGA, which needs to be enabled early, so the VGA_EN is set along the bridges, and PCI K8 resource maps are set correctly. Finally the CPU accessible framebuffer is now disabled as it is not needed.
Signed-off-by: Rudolf Marek r.marek@assembler.cz
Rudolf