Hi,
I've bought two 4G DIMMs with the following characteristics: - Vendor: Corsair - Model: MACMEMORY - Markings: CMSA4GX3M1A1066C7 DDR3 <A serial number> - Chips markings: Corsair 256MB8DCJG HYE0001924
On a Thinkpad X200 with coreboot master, it gives me the following log:
coreboot-4.10-678-gdd12d53494b-dirty Mon Sep 16 13:42:10 UTC 2019 romstage starting (log level: 8)... Stepping B3 2 CPU cores AMT enabled capable of DDR2 of 800 MHz or lower VT-d enabled GMCH: GM45 TXT enabled Render frequency: 533 MHz IGD enabled PCIe-to-GMCH enabled GMCH supports DDR3 with 1067 MT or less GMCH supports FSB with up to 1067 MHz SMBus controller enabled. 0:50:b 2:51:b DDR mask 5, DDR 3 Bank 0 populated: Raw card type: D Row addr bits: 15 Col addr bits: 10 byte width: 1 page size: 1024 banks: 8 ranks: 2 tAAmin: 105 tCKmin: 15 Max clock: 533 MHz CAS: 0x01c0 Bank 1 populated: Raw card type: D Row addr bits: 15 Col addr bits: 10 byte width: 1 page size: 1024 banks: 8 ranks: 2 tAAmin: 105 tCKmin: 15 Max clock: 533 MHz CAS: 0x01c0 Trying CAS 7, tCK 15. Found compatible clock / CAS pair: 533 / 7. Timing values: tCLK: 15 tRAS: 20 tRP: 7 tRCD: 7 tRFC: 104 tWR: 8 tRD: 11 tRRD: 4 tFAW: 20 tWL: 6 Setting IGD memory frequencies for VCO #1. Memory configured in dual-channel assymetric mode. Memory map: TOM = 512MB TOLUD = 512MB TOUUD = 512MB REMAP: base = 65535MB limit = 0MB usedMEsize: 0MB JEDEC init @0x00000000 JEDEC init @0x08000000 JEDEC init @0x10000000 JEDEC init @0x18000000 Final timings for group 0, ch 0: 7.0.0.3.7 Final timings for group 1, ch 0: 7.0.0.3.2 Final timings for group 2, ch 0: 7.0.2.3.1 Final timings for group 3, ch 0: 7.0.2.1.3 Final timings for group 0, ch 1: 7.0.0.1.1 Final timings for group 1, ch 1: 7.4.0.7.1 Final timings for group 2, ch 1: 7.0.2.0.6 Final timings for group 3, ch 1: 7.0.0.8.3 Lower bound for byte lane 0, ch 0: 0.0 Upper bound for byte lane 0, ch 0: 10.5 Final timings for byte lane 0, ch 0: 5.2 Lower bound for byte lane 1, ch 0: 0.0 Upper bound for byte lane 1, ch 0: 9.3 Final timings for byte lane 1, ch 0: 4.5 Lower bound for byte lane 2, ch 0: 0.0 Upper bound for byte lane 2, ch 0: 10.0 Final timings for byte lane 2, ch 0: 5.0 Lower bound for byte lane 3, ch 0: 0.0 Upper bound for byte lane 3, ch 0: 10.3 Final timings for byte lane 3, ch 0: 5.1 Timing overflow during read training. Read training failure: lower bound.
On older Coreboot versions it failed as well.
With other known-working DIMMs I can manage to get pass this stage and the laptop gets up to ramstage:
usbdebug: ramstage starting...
However for some other reason it doesn't boot, but that's probably for another mail.
Denis.