Author: oxygene Date: Tue Oct 5 15:40:31 2010 New Revision: 5911 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5911
Log: - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead
Signed-off-by: Patrick Georgi patrick.georgi@coresystems.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/include/ehci.h trunk/src/include/usbdebug.h trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/pc80/usbdebug_serial.c trunk/src/southbridge/amd/sb600/Kconfig trunk/src/southbridge/amd/sb600/Makefile.inc trunk/src/southbridge/amd/sb600/sb600.h trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c trunk/src/southbridge/amd/sb700/Kconfig trunk/src/southbridge/amd/sb700/Makefile.inc trunk/src/southbridge/amd/sb700/sb700.h trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c trunk/src/southbridge/intel/i82801gx/Kconfig trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c trunk/src/southbridge/nvidia/ck804/Kconfig trunk/src/southbridge/nvidia/ck804/Makefile.inc trunk/src/southbridge/nvidia/ck804/ck804.h trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c trunk/src/southbridge/nvidia/mcp55/Kconfig trunk/src/southbridge/nvidia/mcp55/Makefile.inc trunk/src/southbridge/nvidia/mcp55/mcp55.h trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c trunk/src/southbridge/sis/sis966/Kconfig trunk/src/southbridge/sis/sis966/Makefile.inc trunk/src/southbridge/sis/sis966/sis966.h trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
Modified: trunk/src/include/ehci.h ============================================================================== --- trunk/src/include/ehci.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/include/ehci.h Tue Oct 5 15:40:31 2010 (r5911) @@ -23,6 +23,8 @@ #ifndef EHCI_H #define EHCI_H
+#define EHCI_BAR_INDEX 0x10 + /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
/* Section 2.2 Host Controller Capability Registers */
Modified: trunk/src/include/usbdebug.h ============================================================================== --- trunk/src/include/usbdebug.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/include/usbdebug.h Tue Oct 5 15:40:31 2010 (r5911) @@ -41,6 +41,7 @@ void set_ehci_debug(unsigned ehci_deug); unsigned get_ehci_debug(void); void set_debug_port(unsigned port); +void early_usbdebug_init(void); void usbdebug_ram_tx_byte(unsigned char data); void usbdebug_tx_byte(unsigned char data);
Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,10 +51,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c"
-#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/mahogany/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -50,11 +50,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h>
Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/pistachio/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -45,11 +45,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h>
Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,11 +51,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h>
Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/getac/p470/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -27,6 +27,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <usbdebug.h>
#include <pc80/mc146818rtc.h>
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,13 +51,11 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/sis/sis966/sis966_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include <cpu/amd/model_fxx_rev.h>
+#include "southbridge/sis/sis966/sis966.h" #include "southbridge/sis/sis966/sis966_early_smbus.c" #include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h"
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -49,10 +49,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -55,11 +55,7 @@ static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h>
Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h>
Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/ibase/mb899/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> +#include <usbdebug.h> #include <cpu/x86/bist.h>
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -62,11 +62,7 @@ static int smbus_read_byte(u32 device, u32 address);
#include "superio/fintek/f71859/f71859_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h>
Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> +#include <usbdebug.h> #include <cpu/x86/bist.h>
#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -66,10 +66,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif
-#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h>
Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <usbdebug.h>
#include "superio/winbond/w83627thg/w83627thg.h"
Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/kontron/kt690/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -53,10 +53,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
-#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -52,10 +52,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h"
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -42,10 +42,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <lib.h>
#include <cpu/amd/model_10xxx_rev.h>
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -49,10 +49,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> +#include <usbdebug.h> #include <cpu/x86/bist.h>
#include "northbridge/intel/i945/i945.h"
Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,11 +51,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,11 +51,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -49,11 +49,8 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif #include <lib.h> +#include <usbdebug.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -42,10 +42,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <lib.h>
#include <cpu/amd/model_10xxx_rev.h>
Modified: trunk/src/pc80/usbdebug_serial.c ============================================================================== --- trunk/src/pc80/usbdebug_serial.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/pc80/usbdebug_serial.c Tue Oct 5 15:40:31 2010 (r5911) @@ -19,13 +19,15 @@ */
#include "../lib/usbdebug.c" +#include <arch/io.h> +#include <ehci.h>
-static void early_usbdebug_init(void) +void early_usbdebug_init(void) { struct ehci_debug_info *dbg_info = (struct ehci_debug_info *) (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info));
- usbdebug_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info); + usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); }
void usbdebug_tx_byte(unsigned char data)
Modified: trunk/src/southbridge/amd/sb600/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb600/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -22,3 +22,11 @@ select IOAPIC select HAVE_USBDEBUG
+config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB600 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB600 +
Modified: trunk/src/southbridge/amd/sb600/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/sb600/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -8,3 +8,4 @@ driver-y += sb600_ac97.c driver-y += sb600_pci.c ramstage-y += sb600_reset.c +romstage-y += sb600_enable_usbdebug.c
Modified: trunk/src/southbridge/amd/sb600/sb600.h ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/sb600.h Tue Oct 5 15:40:31 2010 (r5911) @@ -40,4 +40,5 @@ void sb600_lpc_port80(void); void sb600_pci_port80(void);
+void sb600_enable_usbdebug(unsigned int port); #endif /* SB600_H */
Modified: trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -18,12 +18,11 @@ */
#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> - -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ +#include "sb600.h"
/* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -31,7 +30,7 @@ /* TODO: Allow changing the physical USB port used as Debug Port. */ }
-static void sb600_enable_usbdebug(unsigned int port) +void sb600_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
@@ -39,7 +38,7 @@ set_debug_port(port);
/* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
Modified: trunk/src/southbridge/amd/sb700/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb700/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -27,3 +27,11 @@ default n depends on SOUTHBRIDGE_AMD_SB700
+config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB700 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB700 +
Modified: trunk/src/southbridge/amd/sb700/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/sb700/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -7,3 +7,4 @@ driver-y += sb700_hda.c driver-y += sb700_pci.c ramstage-y += sb700_reset.c +romstage-y += sb700_enable_usbdebug.c
Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/sb700.h Tue Oct 5 15:40:31 2010 (r5911) @@ -59,4 +59,5 @@
#endif
+void sb700_enable_usbdebug(unsigned int port); #endif /* SB700_H */
Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -19,14 +19,13 @@ */
#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sb700.h"
-#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ - -#define EHCI_EOR (EHCI_BAR + 0x20) +#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80)
void set_debug_port(unsigned int port) @@ -46,12 +45,12 @@ * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -static void sb700_enable_usbdebug(unsigned int port) +void sb700_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
/* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
Modified: trunk/src/southbridge/intel/i82801gx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/intel/i82801gx/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -24,3 +24,11 @@ select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT
+config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX + +config EHCI_DEBUG_OFFSET + hex + default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX +
Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Oct 5 15:40:31 2010 (r5911) @@ -39,10 +39,13 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0
+#if !defined(ASSEMBLY) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif +void i82801gx_enable_usbdebug(unsigned int port); +#endif
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -18,12 +18,12 @@ */
#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> - -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* Hardwired 0x10 (>= ICH4). */ -#define EHCI_DEBUG_OFFSET 0xA0 /* Hardwired 0xa0 (>= ICH5). */ +#include "i82801gx.h"
/* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -31,20 +31,20 @@ /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ }
-static void i82801gx_enable_usbdebug(unsigned int port) +void i82801gx_enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
/* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */ printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); - dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET); + dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); - write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl); + write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); }
Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -8,3 +8,11 @@ hex default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
+config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 +
Modified: trunk/src/southbridge/nvidia/ck804/Makefile.inc ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -15,5 +15,8 @@
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c
+romstage-y += ck804_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds +
Modified: trunk/src/southbridge/nvidia/ck804/ck804.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/ck804.h Tue Oct 5 15:40:31 2010 (r5911) @@ -4,5 +4,6 @@ #include "chip.h"
void ck804_enable(device_t dev); +void ck804_enable_usbdebug(unsigned int port);
#endif
Modified: trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -22,8 +22,11 @@ */
#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "ck804.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif
-#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ pci_write_config32(dev, 0x74, dword); }
-static void ck804_enable_usbdebug(unsigned int port) +void ck804_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
@@ -55,7 +54,7 @@ set_debug_port(port);
/* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -6,3 +6,12 @@ config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55 +
Modified: trunk/src/southbridge/nvidia/mcp55/Makefile.inc ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -15,5 +15,7 @@
ramstage-y += mcp55_reset.c
+romstage-y += mcp55_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/mcp55.h Tue Oct 5 15:40:31 2010 (r5911) @@ -29,4 +29,5 @@ #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif +void mcp55_enable_usbdebug(unsigned int port); #endif /* MCP55_H */
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -22,8 +22,11 @@ */
#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "mcp55.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif
-#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ pci_write_config32(dev, 0x74, dword); }
-static void mcp55_enable_usbdebug(unsigned int port) +void mcp55_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
@@ -55,7 +54,7 @@ set_debug_port(port);
/* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
Modified: trunk/src/southbridge/sis/sis966/Kconfig ============================================================================== --- trunk/src/southbridge/sis/sis966/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -6,3 +6,11 @@ config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_SIS_SIS966
Modified: trunk/src/southbridge/sis/sis966/Makefile.inc ============================================================================== --- trunk/src/southbridge/sis/sis966/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -9,6 +9,7 @@ driver-y += sis966_pcie.c driver-y += sis966_aza.c ramstage-y += sis966_reset.c +romstage-y += sis966_enable_usbdebug.c
chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds
Modified: trunk/src/southbridge/sis/sis966/sis966.h ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/sis966.h Tue Oct 5 15:40:31 2010 (r5911) @@ -32,5 +32,6 @@ #include "chip.h"
void sis966_enable(device_t dev); +void sis966_enable_usbdebug(unsigned int port);
#endif /* SIS966_H */
Modified: trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -24,8 +24,11 @@ /* TODO: Check whether this actually works (might be copy-paste leftover). */
#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sis966.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -33,10 +36,6 @@ #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif
-#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -49,7 +48,7 @@ pci_write_config32(dev, 0x74, dword); }
-static void sis966_enable_usbdebug(unsigned int port) +void sis966_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
@@ -57,7 +56,7 @@ set_debug_port(port);
/* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);