Author: stepan Date: 2007-11-02 10:48:14 +0100 (Fri, 02 Nov 2007) New Revision: 2926
Added: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c Log: This patch fixes the superio of the khepri 2100e as detected:
superiotool r2922 Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e
Don't use the non-working trident driver for the blade3d (onboard vga in the rom emulator has not been tested either)
It also adds some preliminary CAR support to the board, so it has a chance to build again.
This board was broken since a couple of months, and the changes are minimal, so I consider this a trivial change -- It doesn't change anything that was used, obviously
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb 2007-11-02 00:31:11 UTC (rev 2925) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb 2007-11-02 09:48:14 UTC (rev 2926) @@ -47,8 +47,27 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o
-dir /drivers/trident/blade3d +if USE_DCACHE_RAM
+if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else + ## ## Romcc output ## @@ -71,14 +90,28 @@ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end
+end + ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/x86/16bit/entry16.inc +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds
+if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + ## ## Build our reset vector (This is where linuxBIOS is entered) ## @@ -91,23 +124,36 @@ end
### Should this be in the northbridge code? +if USE_DCACHE_RAM +else mainboardinit arch/i386/lib/cpu_reset.inc - +end ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds
+if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end +end
### ### O.k. We aren't just an intermediary anymore! @@ -116,6 +162,20 @@ ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## + mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -123,13 +183,22 @@ mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc
-## -## Include the secondary Configuration files -## -dir /pc80 +end + config chip.h
+# FIXME: ROM for onboard VGA + chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end + end + device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT 0 @@ -148,36 +217,45 @@ device pci 1.0 on end end device pci 1.0 on - chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end end device pci 1.1 on end @@ -201,13 +279,5 @@ device pci 19.3 on end end end - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end end
Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb 2007-11-02 00:31:11 UTC (rev 2925) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb 2007-11-02 09:48:14 UTC (rev 2926) @@ -7,6 +7,7 @@ uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP uses FALLBACK_SIZE @@ -18,6 +19,7 @@ uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD uses PAYLOAD_SIZE uses _ROMBASE uses XIP_ROM_SIZE @@ -31,6 +33,8 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses LINUXBIOS_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD @@ -40,11 +44,20 @@ uses MAXIMUM_CONSOLE_LOGLEVEL uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC uses OBJCOPY +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses HW_MEM_HOLE_SIZEK
+uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT
### @@ -59,6 +72,8 @@ ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## +#default FALLBACK_SIZE=131072 +#256K default FALLBACK_SIZE=0x40000
## @@ -75,7 +90,7 @@ ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default IRQ_SLOT_COUNT=15
## ## Build code to export an x86 MP table @@ -100,10 +115,30 @@ ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_LOGICAL_CPUS=1
+#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 + +#1G memory hole +default HW_MEM_HOLE_SIZEK=0x100000 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + + ## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=0 + +## ## Build code to setup a generic IOAPIC ## default CONFIG_IOAPIC=1 @@ -113,6 +148,8 @@ ## default MAINBOARD_PART_NUMBER="Khepri" default MAINBOARD_VENDOR="Newisys" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
### ### LinuxBIOS layout values @@ -157,6 +194,11 @@ default HOSTCC="gcc"
## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## ## The Serial Console ##
Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c 2007-11-02 00:31:11 UTC (rev 2925) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c 2007-11-02 09:48:14 UTC (rev 2926) @@ -19,11 +19,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/model_fxx_rev.h> -#include "superio/nsc/pc87360/pc87360_early_serial.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h"
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void) { @@ -115,7 +115,7 @@ k8_init_and_stop_secondaries(); } /* Setup the console */ - pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init();
Added: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2007-11-02 09:48:14 UTC (rev 2926) @@ -0,0 +1,249 @@ +/* + * This code is derived from the Tyan s2882 cache_as_ram_auto.c + * Adapted by Stefan Reinauer stepan@coresystems.de + * Additional (C) 2007 coresystems GmbH + */ +#define ASSEMBLY 1 +#define __ROMCC__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" + +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + +#include <cpu/amd/model_fxx_rev.h> + +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" + +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + } + else { + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + } +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); + } +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define QRANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + + /* newisys khepri does not want the default */ +#include "resourcemap.c" + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif +#include "cpu/amd/dualcore/dualcore.c" + + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + + +#if USE_FALLBACK_IMAGE == 1 + +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the ck804 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ +// post_code(0x22); + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: +// post_code(0x23); + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ); + + fallback_image: +// post_code(0x25); + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); + +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + (0xa<<3)|0, (0xa<<3)|2, 0, 0, + (0xa<<3)|1, (0xa<<3)|3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + (0xa<<3)|4, (0xa<<3)|6, 0, 0, + (0xa<<3)|5, (0xa<<3)|7, 0, 0, +#endif + }; + + int needs_reset; + unsigned bsp_apicid = 0; + + struct mem_controller ctrl[8]; + unsigned nodes; + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx); + } + +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_khepri_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + needs_reset = setup_coherent_ht_domain(); + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + needs_reset |= ht_setup_chains_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + + enable_smbus(); + + memreset_setup(); + sdram_initialize(nodes, ctrl); + +#if 0 + dump_pci_devices(); +#endif + + post_cache_as_ram(); + +}