On Tue, Mar 4, 2008 at 2:08 AM, Feng, Libo Libo.Feng@amd.com wrote:
In LB stage, only PIC mode is applied, isn't it? However, I remember some people of LB community told me there was no ISR except the debug ISR during LB. So does this mean it totally unnecessary to setup PIC via C00h/C001h IO port in LB?
PIC is set up in many mainboards so it is ready for the kernel. This is because so many $PIR tables are wrong.
PIC is not needed for ISR, but coreboot only does ISR for the case of running PCI (or VGA) ROMs anyway.
APIC is setup only after OS runs and gets the interrupt routing from MPTable or ACPI table, is it correct? Then, what difference between APIC and XAPIC? Some documents say APIC has MMIO space registers at FEC00000h while XAPIC has PCI configuration space registers. But some documents seems to refer the same controller by APIC and XAPIC.
APIC is set up by kernel.
ron