Author: uwe Date: Thu Oct 14 01:00:41 2010 New Revision: 5951 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5951
Log: Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.
This is pretty much the same mechanism as in r5929.
- Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c into distinct compilation units, and don't #include the files anymore in romstage.c files.
- Ditto for northbridge/intel/i82810/raminit.c, and northbridge/intel/i82810/debug.c.
- Add various header files which are now needed, drop unused includes.
- Make functions that need to be visible non-static.
Abuild-tested.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/ecs/p6iwp-fe/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/intel/d810e2cb/romstage.c trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/northbridge/intel/i82810/Makefile.inc trunk/src/northbridge/intel/i82810/debug.c trunk/src/northbridge/intel/i82810/i82810.h trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82810/raminit.h trunk/src/southbridge/intel/i82801ax/Makefile.inc trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h trunk/src/southbridge/intel/i82801bx/Makefile.inc trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h
Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/asus/mew-am/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -23,22 +23,20 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" -#include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -46,7 +44,7 @@ console_init(); report_bist_failure(bist); enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable();
Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,23 +22,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" -#include "lib/debug.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "lib/delay.c" -#include "northbridge/intel/i82810/raminit.c" -#include "northbridge/intel/i82810/debug.c" #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Modified: trunk/src/mainboard/ecs/p6iwp-fe/romstage.c ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/ecs/p6iwp-fe/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -24,20 +24,18 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" -#include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "northbridge/intel/i82810/raminit.c" -#include "northbridge/intel/i82810/debug.c" #include <lib.h>
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { it8712f_24mhz_clkin();
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -31,15 +31,16 @@ /* TODO: It's i810E actually! */ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "lib/debug.c" -#include "northbridge/intel/i82810/raminit.c" #include <lib.h>
/* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { /* TODO: It's a PC87364 actually! */ @@ -48,7 +49,7 @@ console_init(); enable_smbus(); report_bist_failure(bist); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable();
Modified: trunk/src/mainboard/intel/d810e2cb/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/intel/d810e2cb/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -23,24 +23,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82801bx/i82801bx.h" -#include "southbridge/intel/i82801bx/i82801bx_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" -#include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ @@ -52,7 +49,7 @@
report_bist_failure(bist); enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable();
Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -23,22 +23,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -47,7 +46,7 @@
report_bist_failure(bist); enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable();
Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/msi/ms6178/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,21 +22,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "lib/debug.c" -#include "northbridge/intel/i82810/raminit.c" #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { /* FIXME */ @@ -48,12 +48,9 @@
uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable();
Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,20 +22,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "northbridge/intel/i82810/raminit.c" #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -43,7 +44,7 @@ console_init(); enable_smbus(); report_bist_failure(bist); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable();
Modified: trunk/src/northbridge/intel/i82810/Makefile.inc ============================================================================== --- trunk/src/northbridge/intel/i82810/Makefile.inc Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/Makefile.inc Thu Oct 14 01:00:41 2010 (r5951) @@ -20,3 +20,6 @@
driver-y += northbridge.c
+romstage-y += raminit.c +romstage-y += debug.c +
Modified: trunk/src/northbridge/intel/i82810/debug.c ============================================================================== --- trunk/src/northbridge/intel/i82810/debug.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/debug.c Thu Oct 14 01:00:41 2010 (r5951) @@ -1,4 +1,6 @@ -static void dump_spd_registers(void) +#include "raminit.h" + +void dump_spd_registers(void) { #if CONFIG_DEBUG_RAM_SETUP int i;
Modified: trunk/src/northbridge/intel/i82810/i82810.h ============================================================================== --- trunk/src/northbridge/intel/i82810/i82810.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/i82810.h Thu Oct 14 01:00:41 2010 (r5951) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_INTEL_I82810_I82810_H +#define NORTHBRIDGE_INTEL_I82810_I82810_H + /* * Datasheet: * - Name: Intel 810 Chipset: @@ -43,3 +46,7 @@ #define MISSC 0x72 /* Miscellaneous Control */ #define MISSC2 0x80 /* Miscellaneous Control 2 */ #define BUFF_SC 0x92 /* System Memory Buffer Strength Control */ + +int smbus_read_byte(u8 device, u8 address); + +#endif
Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/raminit.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,7 +22,13 @@
#include <spd.h> #include <delay.h> +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h> #include "i82810.h" +#include "raminit.h"
/*----------------------------------------------------------------------------- Macros and definitions. @@ -421,7 +427,7 @@ Public interface. -----------------------------------------------------------------------------*/
-static void sdram_set_registers(void) +void sdram_set_registers(void) { u8 reg8; u16 did; @@ -454,7 +460,7 @@ pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8); }
-static void sdram_set_spd_registers(void) +void sdram_set_spd_registers(void) { spd_set_dram_size(); set_dram_buffer_strength(); @@ -464,7 +470,7 @@ /** * Enable SDRAM. */ -static void sdram_enable(void) +void sdram_enable(void) { int i;
Modified: trunk/src/northbridge/intel/i82810/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/raminit.h Thu Oct 14 01:00:41 2010 (r5951) @@ -27,4 +27,10 @@ /* DIMM0 is at 0x50, DIMM1 is at 0x51. */ #define DIMM_SPD_BASE 0x50
-#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */ +/* Function prototypes. */ +void sdram_set_registers(void); +void sdram_set_spd_registers(void); +void sdram_enable(void); +void dump_spd_registers(void); + +#endif
Modified: trunk/src/southbridge/intel/i82801ax/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801ax/Makefile.inc Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801ax/Makefile.inc Thu Oct 14 01:00:41 2010 (r5951) @@ -29,3 +29,5 @@ ramstage-y += i82801ax_reset.c ramstage-y += i82801ax_watchdog.c
+romstage-y += i82801ax_early_smbus.c +
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Thu Oct 14 01:00:41 2010 (r5951) @@ -20,11 +20,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include "i82801ax.h" #include "i82801ax_smbus.h"
-static void enable_smbus(void) +int smbus_read_byte(u8 device, u8 address); + +void enable_smbus(void) { device_t dev;
@@ -50,7 +56,7 @@ print_debug("SMBus controller enabled\n"); }
-static inline int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(u8 device, u8 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); }
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Thu Oct 14 01:00:41 2010 (r5951) @@ -20,6 +20,9 @@
#include <device/smbus_def.h>
+void enable_smbus(void); +int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address); + static void smbus_delay(void) { inb(0x80); @@ -51,8 +54,7 @@ return loops ? 0 : -1; }
-static int do_smbus_read_byte(u16 smbus_io_base, unsigned device, - unsigned address) +int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) { unsigned char global_status_register; unsigned char byte;
Modified: trunk/src/southbridge/intel/i82801bx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801bx/Makefile.inc Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801bx/Makefile.inc Thu Oct 14 01:00:41 2010 (r5951) @@ -30,3 +30,5 @@ ramstage-y += i82801bx_reset.c ramstage-y += i82801bx_watchdog.c
+romstage-y += i82801bx_early_smbus.c +
Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Thu Oct 14 01:00:41 2010 (r5951) @@ -20,11 +20,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include "i82801bx.h" #include "i82801bx_smbus.h"
-static void enable_smbus(void) +int smbus_read_byte(u8 device, u8 address); + +void enable_smbus(void) { device_t dev;
@@ -50,7 +56,7 @@ print_debug("SMBus controller enabled\n"); }
-static inline int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(u8 device, u8 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); }
Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Thu Oct 14 01:00:41 2010 (r5951) @@ -20,6 +20,8 @@
#include <device/smbus_def.h>
+void enable_smbus(void); + static void smbus_delay(void) { inb(0x80); @@ -51,8 +53,7 @@ return loops ? 0 : -1; }
-static int do_smbus_read_byte(u16 smbus_io_base, unsigned device, - unsigned address) +static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) { unsigned char global_status_register; unsigned char byte;