On 09.05.2017 17:19, Aaron Durbin via coreboot wrote:
On Tue, May 9, 2017 at 10:14 AM, Nico Huber nico.huber@secunet.com wrote:
Hi,
I was walking through the Skylake FSP1.1 support in coreboot and asked myself if it is worth to clean it up and maintain the code? given that the upcoming release of Kabylake FSP should be able to supersede it (I presume it is?). Are there any plans yet to drop it once the next FSP is released? (when will that be anyway?)
I wanted to get rid of it, but Intel claimed they had customers using it still.
Hmmm, if we touch the interface of the FSP driver, any downstream board port that wants to keep track of upstream would have to be updated any- way. Would be nice to know what these customers expect, and when and why they synchronize with upstream.
Btw. does anybody feel like a maintainer for soc/intel/skylake/?
Personally feel? Or want?
You mean if I'm interested? No, not atm. Would also depend on what this discussion will lead to. I was actually asking more if I missed to CC somebody.
Nico
In it's current state it's very hard to use from a mainboard porter's point of view. Many of the selectable Kconfig settings are useless (either don't compile or don't run) for FSP1.1, and there's a `struct pei_data` [1] that seems to be a remnant of compatibility for a dif- ferent blob ;)
That's just an old remnant of passing data around. It could be removed as you annotated isolating those pieces to different structs and/or variables for passing data around. The name is obviously not applicable w.r.t. its current use.
Best regards, Nico
PS. Microcode updates are also missing in the upstream blobs repo. Is that a licensing problem? If I try to download them from Intel, it asks me to click to accept that I'll prevent further distribution. I could prepare a patch to add them but somebody else would have to sign it off.