* repository service svn@coreboot.org [110604 17:45]:
Author: stuge Date: Sat Jun 4 17:45:12 2011 New Revision: 6627 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
Log: Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com Acked-by: Peter Stuge peter@stuge.se
Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
--- trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:44:54 2011 (r6626) +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:45:12 2011 (r6627) @@ -50,6 +50,13 @@ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0);
- // early enable of PrefetchEnSPIFromHost
- if (boot_cpu())
- {
- __outdword (0xcf8, 0x8000a3b8);
- __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
- }
This should use pci config space access functions. Also, enabling Prefetch and 33MHz fast read mode should possibly go in the southbridge's bootblock.c so the first cbfs scan does not run with the slow settings.
// early enable of SPI 33 MHz fast mode read if (boot_cpu()) {