Re: [coreboot] Help with RX serial interrupts?

[Alex G.]

On 02/08/2011 11:32 PM, Votier, Sean (DS-1) wrote:
> Designation:  Non-SSA/Finmeccanica
>
> Thanks for the reply Alex.

I'll do my best to help as much as I can. Though make sure next time you
hit the "reply all" or "reply list" button, as your message didn't make
it to the list.
> No, I'm not totally sure. I've looked through the docs and picked the
> values for the registers that seem appropriate.

There's the problem right there. There is a big difference between
"seems" and "are".
I'm working on a K8T800 board, the southbridge containing the IOAPIC is
already supported, and yet it still doesn't work. Try to rip off as much
data as you can from the mfg BIOS.
That's all I can tell you, I'm not an expert in the field.
> I looked though the core
> boot code to see what was in there but their IRQ scheme it's much more
> complicated than I need and it didn't lend itself well to my particular
> situation. The problem with IRQ's is that they are a bitch to
> troubleshoot, particularly when the signals are all on the silicon so
> you can't put a scope on them :(

Coreboot's scheme is fairly straightforward. To my understanding, it
sets up the IOAPICs as virtual-wire, compliant with the Intel MP spec
(which I read last night :P ). To software, this looks (should look)
just like PIC mode.

Alex
> Sean
>
> -----Original Message-----
> From: coreboot-bounces+svotier=[e-mail]
> [mailto:coreboot-bounces+svotier=[e-mail]] On Behalf Of
> Alex G.
> Sent: Tuesday, February 08, 2011 4:15 PM
> To: [e-mail]
> Subject: Re: [coreboot] Help with RX serial interrupts?
>
> Are you sure it's not just a bad PIC/APIC config?
>
> Alex
>
> On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote:
> > Designation: Non-SSA/Finmeccanica
> >
> > Hi all.
> >
> > I would like to apologise for being a lurker on this list and only 
> > popping up when I need help. But I need help...........
> >
> > I've run into an issue that has been stumping my for the last couple 
> > of weeks.
> >
> > I'm developing bios code for a GE CR-11 Compact PCI board.
> >
> > The chips I'm working with are:
> >
> > 1.06 Mhz Pentium M
> >
> > E7520 Northbridge
> >
> > 6300ESB Southbridge
> >
> > I'm initialising the SIU in the Southbridge. I have the port
>
> configured.
> > I can see data transmitted and received from and to the serial port 
> > using a scope on the serial cable and also on my emulator but I can't 
> > seem to get the receive side to generate an interrupt. Does anyone 
> > have experience with serial interrupts on this hardware? Can you run 
> > through the steps involved for a very simple rx interrupt config just 
> > in case I missed something in the Intel docs. Know of an pitfalls?
>
> 3.1.1001