There are more than a dozen targets in the v2 tree which refer to ROMCC in their Config.lb but never use it. There's no point in keeping dead code around. Kill it.
This patch removes ROMCC remainders from Config.lb for tyan/s2735 and tyan/s2850.
Abuild build log with and without the patch is completely identical.
If this patch is OK, I'll create more of the same type, hopefully making ROMCC dependencies a bit more clear for v2.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/Config.lb (revision 4047) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/Config.lb (working copy) @@ -45,8 +45,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM - if CONFIG_USE_INIT
makerule ./auto.o @@ -64,32 +62,7 @@ end
end -else - ## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - -end -## ## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE @@ -99,7 +72,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -107,7 +79,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end
## ## Build our reset vector (This is where coreboot is entered) @@ -120,24 +91,16 @@ ldscript /cpu/x86/32bit/reset32.lds end
-if USE_DCACHE_RAM -else -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end
### ### This is the early phase of coreboot startup @@ -145,13 +108,8 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE -if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds -else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc end -end
### ### O.k. We aren't just an intermediary anymore! @@ -160,29 +118,13 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end
-else - ## -## Setup RAM -## -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit cpu/x86/sse/enable_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse/disable_sse.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - -## ## Include the secondary Configuration files ## config chip.h Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/Config.lb (revision 4047) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/Config.lb (working copy) @@ -35,7 +35,6 @@
arch i386 end
- ## ## Build the objects we have code for in this directory. ## @@ -44,8 +43,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT
makerule ./auto.o @@ -63,39 +60,13 @@ end
end -else
## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - -end - -## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -103,7 +74,6 @@ if CONFIG_USE_INIT ldscript /cpu/x86/car/cache_as_ram.lds end -end
## @@ -117,24 +87,16 @@ ldscript /cpu/x86/32bit/reset32.lds end
-if USE_DCACHE_RAM -else -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/x86/car/cache_as_ram.inc -end
### ### This is the early phase of coreboot startup @@ -142,36 +104,18 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE -if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds -else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc end -end
## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end
-else -# ROMCC -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit cpu/x86/sse/enable_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse/disable_sse.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - ## ## Include the secondary Configuration files ##