[coreboot] Resource allocator: Getting v4 back in

[Nico Huber]

Hello together,

Furquan has landed his revert series of the new resource allocator. A
little sad, but this allows us to take a deep breath and fix things
without further breakage.

There is already one change series on Gerrit to bring it back [1]. This
one goes the most conservative way: It moves the old allocator code
aside, so we can have two versions in the tree and decide per chipset/
board which one to use.

I told people that I had something similar in mind. But actually, I
don't like it very much. I fear, if we move things aside, they can be
left behind and we might soon have to discuss platform deprecation
again. It would also be harder to make changes in generic code like
device/pci_device when one has to be sure that both allocators work
fine.

So I want to propose alternatives. The obvious one, but also slowest,
is to move all chipset code forward and to test and patch all the code
before we merge the new allocator again. I might underestimate the pro-
blems, but I still think we could get this going within a week.

Another option: we could identify the differences in the new allocator
that had a part in the breakage and only provide a backward compatible
implementation for those. Actually, I think it's only one: the resource
constraining strategy for the domain. To make this compatible, we could
a) drop all but the biggest memrange below 4G for the domain, and
b) assign/steal resources from the end of the memrange at the domain
   level.
It would closely mimic what the old code tried to achieve, so seems
safe, somehow.

I can write patches for the latter, if we want to try this way.

Nico

[1] https://review.coreboot.org/c/coreboot/+/41442/

PS. Had some random thoughts I don't want to forget but didn't know
    where to put them down:
    * Debug messages. There is a lot of BIOS_SPEW (was already like this
      in the old code). Things that are only printed once per pass per
      bridge shouldn't be considered SPEW, IMO.
    * The above-4G memrange should be aligned to a power of 2 for better
      MTRR usage (if that isn't the case already?).