On 7/5/07, Songmao Tian tiansm@lemote.com wrote:
with regard to interrupt signal, I am still puzzled with the PCI_INTA#, it is said that it's a input io. Shouldn't it output the interrupt signal to cpu?
On 5536, the PCI_INT{A,B,C,D}# signals are usually configured as inputs. (they are all just part of the GPIO block). Those signals then get mapped into the interrupt logic through the various IRQ mapping MSRs.
Interrupt delivery to the processor is done on the "CIS" pin that is an output from 5536 to the GX or LX processor. The CIS pin delivers IRQ, SMI, NMI, etc in a serial stream to the CPU. (the CPU de-serializes it, and has internal versions of those signals)
Your goal seems to be to mux 5536's internal INTR signal out onto a GPIO. There are some hints about that in the datasheet, but that is not an official way to do it. Normal Geode systems all use the serial packet. You will probably not get any support from AMD to do it that way, that path is not tested. (though I have seen it work)