#define IDE_CFG 0x40 #define CHANEN (1L << 1) #define PWB (1L << 14) #define CABLE (1L << 16) #define IDE_DTC 0x48 #define IDE_CAST 0x4C #define IDE_ETC 0x50
static void ide_init(struct device *dev) { uint32_t ide_cfg;
printk_spew("cs5536_ide: %s\n", __FUNCTION__); /* GPIO and IRQ setup are handled in the main chipset code. */
// Enable the channel and Post Write Buffer // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set ide_cfg = pci_read_config32(dev, IDE_CFG); ide_cfg |= CHANEN | PWB; pci_write_config8(dev, IDE_CFG, ide_cfg); }
Note the pci_read_config32 followed by the pci_write_config8.
HMM, why did this ever work? Anyway, I changed the write_config8 to write_config32 and it is still no good on the alix1c on v3. If someone wants to try this fix on v2, go for it:
Index: southbridge/amd/cs5536/cs5536.c =================================================================== --- southbridge/amd/cs5536/cs5536.c (revision 676) +++ southbridge/amd/cs5536/cs5536.c (working copy) @@ -597,7 +597,7 @@ // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set ide_cfg = pci_read_config32(dev, IDE_CFG); ide_cfg |= CHANEN | PWB; - pci_write_config8(dev, IDE_CFG, ide_cfg); + pci_write_config32(dev, IDE_CFG, ide_cfg); }
you need to translate for the v2 filename.
off to rest, if somebody gets somewhere with this, let me know.
ron