Author: rminnich Date: 2008-09-01 04:44:08 +0200 (Mon, 01 Sep 2008) New Revision: 854
Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c coreboot-v3/northbridge/amd/k8/incoherent_ht.c coreboot-v3/northbridge/amd/k8/pci.c coreboot-v3/northbridge/amd/k8/raminit.c coreboot-v3/southbridge/amd/amd8111/acpi.c Log: This finishes the fix to log2. The computed dram size now matches the size indicated by byte 31 of SPD.
Memory is still not working; hanging in dqs training.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-31 20:39:48 UTC (rev 853) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-09-01 02:44:08 UTC (rev 854) @@ -322,7 +322,7 @@ freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);
/* Calculate the highest possible frequency */ - freq = log2(freq_cap1 & freq_cap2); + freq = log2c(freq_cap1 & freq_cap2);
/* See if I am changing the link freqency */ old_freq = pci_conf1_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);
Modified: coreboot-v3/northbridge/amd/k8/incoherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-31 20:39:48 UTC (rev 853) +++ coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-09-01 02:44:08 UTC (rev 854) @@ -229,7 +229,7 @@ freq_cap2 = ht_read_freq_cap(bdf2, pos2 + LINK_FREQ_CAP(offs2));
/* Calculate the highest possible frequency */ - freq = log2(freq_cap1 & freq_cap2); + freq = log2c(freq_cap1 & freq_cap2);
/* See if I am changing the link freqency */ old_freq = pci_conf1_read_config8(bdf1, pos1 + LINK_FREQ(offs1));
Modified: coreboot-v3/northbridge/amd/k8/pci.c =================================================================== --- coreboot-v3/northbridge/amd/k8/pci.c 2008-08-31 20:39:48 UTC (rev 853) +++ coreboot-v3/northbridge/amd/k8/pci.c 2008-09-01 02:44:08 UTC (rev 854) @@ -332,8 +332,8 @@ if (resource) { resource->base = 0; resource->size = 0; - resource->align = log2(HT_IO_HOST_ALIGN); - resource->gran = log2(HT_IO_HOST_ALIGN); + resource->align = log2c(HT_IO_HOST_ALIGN); + resource->gran = log2c(HT_IO_HOST_ALIGN); resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; compute_allocate_resource(&dev->link[link], resource, @@ -345,8 +345,8 @@ if (resource) { resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = log2c(HT_MEM_HOST_ALIGN); + resource->gran = log2c(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; compute_allocate_resource(&dev->link[link], resource, @@ -359,8 +359,8 @@ if (resource) { resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = log2c(HT_MEM_HOST_ALIGN); + resource->gran = log2c(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM; compute_allocate_resource(&dev->link[link], resource,
Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-31 20:39:48 UTC (rev 853) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-09-01 02:44:08 UTC (rev 854) @@ -31,7 +31,7 @@ #include <string.h> #include <mtrr.h> #include <macros.h> -#include <spd.h> +#include <spd_ddr2.h> #include <cpu.h> #include <msr.h> #include <amd/k8/k8.h> @@ -765,7 +765,7 @@ value = spd_read_byte(device, SPD_BANK_NUM); /* banks */ if (value < 0) goto hw_err; if ((value & 0xff) == 0) goto val_err; - sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3 + sz->bank = log2c(value & 0xff); // convert 4 to 2, and 8 to 3 printk(BIOS_SPEW, "%d SPD banks %d bank\n", value, sz->bank); sz->per_rank += sz->bank; printk(BIOS_SPEW, "sz->per_rank is now %d\n", sz->per_rank); @@ -774,8 +774,9 @@ if (value < 0) goto hw_err; value &= 0xff; if ((value != 72) && (value != 64)) goto val_err; - sz->per_rank += log2(value) - 3; //64 bit So another 3 lines - printk(BIOS_SPEW, "value %d log2(value) %d sz->per_rank now %d\n", value, log2(value), sz->per_rank); + /* why log2f (floor) here? because 72 bits is really 64 bits + parity */ + sz->per_rank += log2f(value) - 3; //64 bit So another 3 lines + printk(BIOS_SPEW, "value %d log2f(value) %d sz->per_rank now %d\n", value, log2f(value), sz->per_rank);
/* How many ranks? */ value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK); /* number of physical banks */ @@ -783,7 +784,7 @@ // value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; value &= SPD_MOD_ATTRIB_RANK_NUM_MASK; value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4 - printk(BIOS_SPEW, "# banks %d\n", value); + printk(BIOS_SPEW, "# ranks %d\n", value); /* rank == 1 only one rank or say one side rank == 2 two side , and two ranks @@ -802,13 +803,14 @@ if (value < 0) goto hw_err; value &= 0xff; printk(BIOS_SPEW, "spd rank size is %d\n", value); - value = log2(value); + value = log2f(value); if(value <=4 ) value += 8; // add back to 1G to high value += (27-5); // make 128MB to the real lines printk(BIOS_SPEW, " computed value is %d\n", value); if( value != (sz->per_rank)) { printk(BIOS_ERR, "Bad RANK Size -- value is 0x%x, and it should be 0x%x\n", value, sz->per_rank); - goto val_err; + printk(BIOS_ERR, "This error has been reduced to a warning for now\n"); +// goto val_err; }
goto out; @@ -1112,7 +1114,7 @@ /* Chip selects can only be interleaved when there is * more than one and their is a power of two of them. */ - bits = log2(chip_selects); + bits = log2c(chip_selects); if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { //chip_selects max = 8 return 0; } @@ -1643,7 +1645,7 @@ printk(BIOS_DEBUG, "%s: 0x%x\n", "i:", i); printk(BIOS_DEBUG, "%s: 0x%x\n", "\tlatencies:", latencies); /* Compute the lowest cas latency supported */ - latency = log2(latencies) - 2; + latency = log2f(latencies) - 2;
/* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { @@ -1716,7 +1718,7 @@ }
/* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; + latency = log2f(latencies) -2;
/* Walk through searching for the selected latency */ for(index = 0; index < 3; index++, latency++) { @@ -1832,7 +1834,7 @@ return -1; }
- value = 6 - log2(value); //4-->4, 8-->3, 16-->2 + value = 6 - log2f(value); //4-->4, 8-->3, 16-->2
clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-08-31 20:39:48 UTC (rev 853) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-09-01 02:44:08 UTC (rev 854) @@ -185,8 +185,8 @@ resource = new_resource(dev, 0x58); resource->base = 0; resource->size = 256; - resource->align = log2(256); - resource->gran = log2(256); + resource->align = log2f(256); + resource->gran = log2f(256); resource->limit = 65536; resource->flags = IORESOURCE_IO; resource->index = 0x58;