Stephan,
I have checked the AMD sheet, and you are right it will not change to setting width and speed without reset or LDTSTOP_L. In the pci_device.c, there is some code about HT. I have removed the hardcode about width and speed and do some test, after I checked the REG, and it seems width is set right but the speed is not right. Maybe Eric need to check that part.
PS: - PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000, + PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00050000, [..] - PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000, + PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00030000,
should be there. It defines the bus number behind the links. It will be used when enumerating the non-coherent devices.
Regards
YH
-----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年8月28日 7:40 收件人: linuxbios@clustermatic.org 主题: Re: Unified setup...
Hi again,
the coherent_ht.c changes are all to LYH's hardcodes to coherent_ht_finalize(). These are there to setup link speed and width on the cht nodes.
I remember tomz from LNXI was working on that on a higher level at pci setup. Is that code complete by now? Are all bridges set up full speed?
Then we could just drop this code, which i would favour. Otherwise it should walk into the motherboard specific code.
As far as I can see this code is noop anyways since speed changes need a reset or LDTSTOP_L which is not asserted here. LYH, any comments?
--- coherent_ht.c 2003-08-14 11:11:10.000000000 +0200 +++ coherent_ht.1.c 2003-08-28 06:42:50.000000000 +0200 [..] - PCI_ADDR(0, 0x18, 0, 0xc4), 0x88ff9c05, 0x770000d0, + PCI_ADDR(0, 0x18, 0, 0xc4), 0x88ff9c05, 0x11000020, [..] - PCI_ADDR(0, 0x18, 0, 0xc8), 0xfffff0ff, 0x00000000, + PCI_ADDR(0, 0x18, 0, 0xc8), 0xfffff0ff, 0x00000400, [..] - PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000, + PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00050000, [..] - PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000, + PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00030000,
Stefan