Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/295
-gerrit
commit 3088f1891acd7bef8bdee3c1fa0e26041ea2d597 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Oct 31 14:18:33 2011 +0200
Add support for E7505 northbridge.
Adapted from northbridge/intel/e7501 with only minor changes. This commit provides minimal patch from e7501 and I prefer any cosmetic clean-up to be done after initial merge.
Due the incomplete register specifications, it is safer to have e7505 as a separate directory in case I improve it to support wider range of memory configurations. I have no e7501 to test with.
Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/e7505/Kconfig | 2 +- src/northbridge/intel/e7505/chip.h | 5 +- src/northbridge/intel/e7505/debug.c | 32 ++-- src/northbridge/intel/e7505/e7501.h | 79 --------- src/northbridge/intel/e7505/e7505.h | 79 +++++++++ src/northbridge/intel/e7505/northbridge.c | 29 +++- src/northbridge/intel/e7505/raminit.c | 274 ++++++++++++++++++----------- 9 files changed, 289 insertions(+), 213 deletions(-)
diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 409eb5e..1809d11 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -1,4 +1,5 @@ source src/northbridge/intel/e7501/Kconfig +source src/northbridge/intel/e7505/Kconfig source src/northbridge/intel/e7520/Kconfig source src/northbridge/intel/e7525/Kconfig source src/northbridge/intel/i3100/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 266f6f8..0d116d0 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -1,4 +1,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7520) += e7520 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100 diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index c8219e8..578ab86 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -1,4 +1,4 @@ -config NORTHBRIDGE_INTEL_E7501 +config NORTHBRIDGE_INTEL_E7505 bool select HAVE_DEBUG_RAM_SETUP
diff --git a/src/northbridge/intel/e7505/chip.h b/src/northbridge/intel/e7505/chip.h index 458510b..9677dca 100644 --- a/src/northbridge/intel/e7505/chip.h +++ b/src/northbridge/intel/e7505/chip.h @@ -1,5 +1,6 @@ -struct northbridge_intel_e7501_config +struct northbridge_intel_e7505_config { };
-extern struct chip_operations northbridge_intel_e7501_ops; +extern struct chip_operations northbridge_intel_e7505_ops; + diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index f19de0c..07f1596 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev) for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x:",i); #else print_debug("\n"); @@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev) #endif } val = pci_read_config8(dev, i); -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x", val); #else print_debug_char(' '); @@ -101,7 +101,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); #else print_debug("dimm: "); @@ -113,7 +113,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); @@ -126,7 +126,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) break; } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -138,7 +138,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else print_debug("dimm: "); @@ -150,7 +150,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); @@ -163,7 +163,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) break; } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -181,7 +181,7 @@ static inline void dump_smbus_registers(void) for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "smbus: %02x", device); #else print_debug("smbus: "); @@ -195,7 +195,7 @@ static inline void dump_smbus_registers(void) break; } if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ",j); #else print_debug("\n"); @@ -204,7 +204,7 @@ static inline void dump_smbus_registers(void) #endif } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -219,7 +219,7 @@ static inline void dump_io_resources(unsigned port) {
int i; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%04x:\n", port); #else print_debug_hex16(port); @@ -228,7 +228,7 @@ static inline void dump_io_resources(unsigned port) for(i=0;i<256;i++) { uint8_t val; if ((i & 0x0f) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x:", i); #else print_debug_hex8(i); @@ -236,7 +236,7 @@ static inline void dump_io_resources(unsigned port) #endif } val = inb(port); -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x",val); #else print_debug_char(' '); @@ -255,7 +255,7 @@ static inline void dump_mem(unsigned start, unsigned end) print_debug("dump_mem:"); for(i=start;i<end;i++) { if((i & 0xf)==0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%08x:", i); #else print_debug("\n"); @@ -263,7 +263,7 @@ static inline void dump_mem(unsigned start, unsigned end) print_debug(":"); #endif } -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" "); diff --git a/src/northbridge/intel/e7505/e7501.h b/src/northbridge/intel/e7505/e7501.h deleted file mode 100644 index 32a26da..0000000 --- a/src/northbridge/intel/e7505/e7501.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * e7501.h: PCI configuration space for the Intel E7501 memory controller - */ - -/************ D0:F0 ************/ -// Register offsets -#define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */ -#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ -#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ -#define DRB_ROW_1 0x61 -#define DRB_ROW_2 0x62 -#define DRB_ROW_3 0x63 -#define DRB_ROW_4 0x64 -#define DRB_ROW_5 0x65 -#define DRB_ROW_6 0x66 -#define DRB_ROW_7 0x67 - -#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ -#define DRT 0x78 /* DRAM Timing register, 32 bit */ -#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ -#define MAYBE_DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ -#define CKDIS 0x8C /* Clock disable register, 8 bit */ -#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ -#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ -#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ -#define SKPD 0xDE /* Scratchpad register, 16 bit */ -#define MAYBE_MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ - -// CAS# Latency bits in the DRAM Timing (DRT) register -#define DRT_CAS_2_5 (0<<4) -#define DRT_CAS_2_0 (1<<4) -#define DRT_CAS_MASK (3<<4) - -// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register -#define RAM_COMMAND_NOP (1<<4) -#define RAM_COMMAND_PRECHARGE (2<<4) -#define RAM_COMMAND_MRS (3<<4) -#define RAM_COMMAND_EMRS (4<<4) -#define RAM_COMMAND_CBR (6<<4) -#define RAM_COMMAND_NORMAL (7<<4) - - -// RCOMP Memory Map offsets -// Conjecture based on apparent similarity between E7501 and 855PM -// Intel doc. 252613-003 describes these for 855PM - -#define MAYBE_SMRCTL 0x20 /* System Memory RCOMP Control Register? */ -#define MAYBE_DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ -#define MAYBE_CKESTR 0x31 /* Strength control for CKE signal group? */ -#define MAYBE_CSBSTR 0x32 /* Strength control for CS# signal group? */ -#define MAYBE_CKSTR 0x33 /* Strength control for CK signal group? */ -#define MAYBE_RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ - -/************ D0:F1 ************/ -// Register offsets -#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */ -#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ -#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ -#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h new file mode 100644 index 0000000..e20c5bc --- /dev/null +++ b/src/northbridge/intel/e7505/e7505.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * e7505.h: PCI configuration space for the Intel E7501 memory controller + */ + +/************ D0:F0 ************/ +// Register offsets +#define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */ +#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ +#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ +#define DRB_ROW_1 0x61 +#define DRB_ROW_2 0x62 +#define DRB_ROW_3 0x63 +#define DRB_ROW_4 0x64 +#define DRB_ROW_5 0x65 +#define DRB_ROW_6 0x66 +#define DRB_ROW_7 0x67 + +#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ +#define DRT 0x78 /* DRAM Timing register, 32 bit */ +#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ +#define MAYBE_DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ +#define CKDIS 0x8C /* Clock disable register, 8 bit */ +#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ +#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ +#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ +#define SKPD 0xDE /* Scratchpad register, 16 bit */ +#define MAYBE_MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ + +// CAS# Latency bits in the DRAM Timing (DRT) register +#define DRT_CAS_2_5 (0<<4) +#define DRT_CAS_2_0 (1<<4) +#define DRT_CAS_MASK (3<<4) + +// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register +#define RAM_COMMAND_NOP (1<<4) +#define RAM_COMMAND_PRECHARGE (2<<4) +#define RAM_COMMAND_MRS (3<<4) +#define RAM_COMMAND_EMRS (4<<4) +#define RAM_COMMAND_CBR (6<<4) +#define RAM_COMMAND_NORMAL (7<<4) + + +// RCOMP Memory Map offsets +// Conjecture based on apparent similarity between E7501 and 855PM +// Intel doc. 252613-003 describes these for 855PM + +#define MAYBE_SMRCTL 0x20 /* System Memory RCOMP Control Register? */ +#define MAYBE_DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ +#define MAYBE_CKESTR 0x31 /* Strength control for CKE signal group? */ +#define MAYBE_CSBSTR 0x32 /* Strength control for CS# signal group? */ +#define MAYBE_CKSTR 0x33 /* Strength control for CK signal group? */ +#define MAYBE_RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ + +/************ D0:F1 ************/ +// Register offsets +#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */ +#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ +#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ +#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index e6e955f..1ea3ce9 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -8,6 +8,7 @@ #include <string.h> #include <bitops.h> #include "chip.h" +#include "e7505.h"
#if CONFIG_WRITE_HIGH_TABLES==1 #include <cbmem.h> @@ -65,17 +66,17 @@ static void pci_domain_set_resources(device_t dev) /* Write the ram configuration registers, * preserving the reserved bits. */ - tolm_r = pci_read_config16(mc_dev, 0xc4); + tolm_r = pci_read_config16(mc_dev, TOLM); tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); - pci_write_config16(mc_dev, 0xc4, tolm_r); + pci_write_config16(mc_dev, TOLM, tolm_r);
- remapbase_r = pci_read_config16(mc_dev, 0xc6); + remapbase_r = pci_read_config16(mc_dev, REMAPBASE); remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); - pci_write_config16(mc_dev, 0xc6, remapbase_r); + pci_write_config16(mc_dev, REMAPBASE, remapbase_r);
- remaplimit_r = pci_read_config16(mc_dev, 0xc8); + remaplimit_r = pci_read_config16(mc_dev, REMAPLIMIT); remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); - pci_write_config16(mc_dev, 0xc8, remaplimit_r); + pci_write_config16(mc_dev, REMAPLIMIT, remaplimit_r);
/* Report the memory regions */ idx = 10; @@ -98,12 +99,23 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, + .ops_pci = &intel_pci_ops, .ops_pci_bus = &pci_cf8_conf1, };
@@ -135,7 +147,8 @@ static void enable_dev(struct device *dev) } }
-struct chip_operations northbridge_intel_e7501_ops = { - CHIP_NAME("Intel E7501 Northbridge") +struct chip_operations northbridge_intel_e7505_ops = { + CHIP_NAME("Intel E7505 Northbridge") .enable_dev = enable_dev, }; + diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index f42bef2..46c1903 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -15,7 +15,7 @@ #include <spd.h> #include <sdram_mode.h> #include <stdlib.h> -#include "e7501.h" +#include "e7505.h"
/*----------------------------------------------------------------------------- Definitions: @@ -176,7 +176,8 @@ static const long constant_register_values[] = { // without jumping through 36-bit adddressing hoops, even if the // total memory is > 4 GB. Changing these values may break do_ram_command()! 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), - 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), +// 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), + 0x64, 0x00000000, (0x04 << 0) | (0x04 << 8) | (0x04 << 16) | (0x04 << 24),
/* DRA - DRAM Row Attribute Register * 0x70 Row 0,1 @@ -260,7 +261,8 @@ static const long constant_register_values[] = {
// The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. - 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16), +// 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16), + 0x78, 0xC7F8FFFF, (0x03<<16)|(0x28<<24),
/* FIXME why was I attempting to set a reserved bit? */ /* 0x0100040f */ @@ -314,7 +316,8 @@ static const long constant_register_values[] = {
// Default to dual-channel mode, ECC, 1-clock address/cmd hold // NOTE: configure_e7501_dram_controller_mode() configures further - 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), +// 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), + 0x7c, 0xffcef8f7, 0x00210008,
/* Another Intel undocumented register * 0x88 - 0x8B @@ -400,7 +403,8 @@ static const long constant_register_values[] = { */
// Enable D0:D1, disable D2:F1, D3:F1, D4:F1 - 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0), +// 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0), + 0xe0, 0xfffffffa, 0x0,
// Undocumented 0xd8, 0xffff9fff, 0x00000000, @@ -422,7 +426,7 @@ static const long constant_register_values[] = { * [00:00] Unknown - not used? */
- 0xf4, 0x3f8ffffd, 0x40300002, +// 0xf4, 0x3f8ffffd, 0x40300002,
#ifdef SUSPICIOUS_LOOKING_CODE // SJM: Undocumented. @@ -432,12 +436,13 @@ static const long constant_register_values[] = { };
/* DDR RECOMP tables */ - +#if 0 // Slew table for 1x drive? static const uint32_t maybe_1x_slew_table[] = { 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff, 0x22111111, 0x55444332, 0xfffca876, 0xffffffff, }; +#endif
// Slew table for 2x drive? static const uint32_t maybe_2x_slew_table[] = { @@ -478,16 +483,64 @@ static void do_delay(void)
#define EXTRA_DELAY DO_DELAY
-static void die_on_spd_error(int spd_return_value) +/*----------------------------------------------------------------------------- +Handle (undocumented) control bits in device 0:6.0 +-----------------------------------------------------------------------------*/ + +/** + * + */ +static void ram_handle_d060_1(void) { - if (spd_return_value < 0) - die("Error reading SPD info\n"); + uint32_t dword; + + dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword |= 0x02; + pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + + dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0); + dword |= 0x04; + pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword); + + dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword &= ~0x02; + pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); +} + +/** + * + */ +static void ram_handle_d060_2(void) +{ + uint32_t dword; + uint8_t revision; + + revision = pci_read_config8(PCI_DEV(0,0,0), 0x08); + if (revision >= 3) { + dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword |= 0x02; + pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + + dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0); + dword |= 0x18000000; + pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword); + + dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword &= ~0x02; + pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + } }
/*----------------------------------------------------------------------------- Serial presence detect (SPD) functions: -----------------------------------------------------------------------------*/
+static void die_on_spd_error(int spd_return_value) +{ + if (spd_return_value < 0) + die("Error reading SPD info\n"); +} + /** * Calculate the page size for each physical bank of the DIMM: * log2(page size) = (# columns) + log2(data width) @@ -843,10 +896,10 @@ SDRAM configuration functions: */ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) { - int i; + uint8_t dimm_start_64M_multiple; + uint32_t dimm_start_address; uint32_t dram_controller_mode; - uint8_t dimm_start_64M_multiple = 0; - uint16_t e7501_mode_bits = jedec_mode_bits; + uint8_t i;
// Configure the RAM command dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); @@ -856,58 +909,43 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
// RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. + if (command == RAM_COMMAND_NORMAL) + return;
- if (command != RAM_COMMAND_NORMAL) { - - // Send the command to all DIMMs by accessing a memory location within each - // NOTE: for mode select commands, some of the location address bits - // are part of the command - - // Map JEDEC mode bits to E7501 - if (command == RAM_COMMAND_MRS) { - // Host address lines [15:5] map to DIMM address lines [12:11, 9:1] - // The E7501 hard-sets DIMM address lines 10 & 0 to zero - - ASSERT(!(jedec_mode_bits & 0x0401)); - - e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) | // JEDEC bits 11-12 move to bits 14-15 - ((jedec_mode_bits & 0x03FE) << (13 - 9)); // JEDEC bits 1-9 move to bits 5-13 - - } else if (command == RAM_COMMAND_EMRS) { - // Host address lines [15:3] map to DIMM address lines [12:0] - e7501_mode_bits = jedec_mode_bits <<= 3; - } else - ASSERT(jedec_mode_bits == 0); - - dimm_start_64M_multiple = 0; - - for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { - - uint8_t dimm_end_64M_multiple = - pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); - if (dimm_end_64M_multiple > dimm_start_64M_multiple) { - - // This code assumes DRAM row boundaries are all set below 4 GB - // NOTE: 0x40 * 64 MB == 4 GB - ASSERT(dimm_start_64M_multiple < 0x40); + // NOTE: for mode select commands, some of the location address bits are part of the command + // Map JEDEC mode bits to E7505 + if (command == RAM_COMMAND_MRS) { + // Host address lines [25:18] map to DIMM address lines [7:0] + // Host address lines [17:16] map to DIMM address lines [9:8] + // Host address lines [15:4] map to DIMM address lines [11:0] + dimm_start_address = (jedec_mode_bits & 0x00ff) << 18; + dimm_start_address |= (jedec_mode_bits & 0x0300) << 8; + dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4; + } else if (command == RAM_COMMAND_EMRS) { + // Host address lines [15:4] map to DIMM address lines [11:0] + dimm_start_address = (jedec_mode_bits << 4); + } else { + ASSERT(jedec_mode_bits == 0); + dimm_start_address = 0; + }
- // NOTE: 2^26 == 64 MB + // Send the command to all DIMMs by accessing a memory location within each
- uint32_t dimm_start_address = - dimm_start_64M_multiple << 26; + dimm_start_64M_multiple = 0;
- RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); - RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); - RAM_DEBUG_MESSAGE("\n"); + for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
- read32(dimm_start_address + e7501_mode_bits); + uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
+ if (dimm_end_64M_multiple > dimm_start_64M_multiple) { + dimm_start_address &= 0x3ffffff; + dimm_start_address |= dimm_start_64M_multiple << 26; + read32(dimm_start_address); // Set the start of the next DIMM - dimm_start_64M_multiple = - dimm_end_64M_multiple; - } + dimm_start_64M_multiple = dimm_end_64M_multiple; } } + }
/** @@ -1136,13 +1174,10 @@ static void initialize_ecc(void) dram_controller_mode >>= 20; dram_controller_mode &= 3; if (dram_controller_mode == 2) { - uint8_t byte;
RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); - /* Initialize ECC bits , use ECC zero mode (new to 7501) */ - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); + pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x01);
// Wait for scrub cycle to complete do { @@ -1150,7 +1185,7 @@ static void initialize_ecc(void) pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); } while ((byte & 0x08) == 0);
- pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); + pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, (byte & 0xfc) | 0x04); RAM_DEBUG_MESSAGE("ECC state initialized.\n");
/* Clear the ECC error bits */ @@ -1160,9 +1195,6 @@ static void initialize_ecc(void) // Clear DRAM Interface error bits (write-one-clear) pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18); pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18); - - // Start normal ECC scrub - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5); }
} @@ -1403,11 +1435,11 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
maybe_dram_read_timing = pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); - maybe_dram_read_timing &= 0xF00C; + maybe_dram_read_timing &= 0xF000;
if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { dram_timing |= DRT_CAS_2_0; - maybe_dram_read_timing |= 0xBB1; + maybe_dram_read_timing |= 0x0222; } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
uint32_t dram_row_attributes = @@ -1438,22 +1470,22 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); dword |= (1 << 26); pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */ - dword |= 0xd2109800; - + /* patch try register 88 is undocumented tnz */ + dword &= 0x0ca17fff; + dword |= 0xd14a5000; pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, maybe_dram_read_timing);
- dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */ + /* clear master DLL reset */ + dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); dword &= ~(1 << 26); pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
return;
- hw_err: +hw_err: die(SPD_ERROR); }
@@ -1627,6 +1659,8 @@ static void enable_e7501_clocks(uint8_t dimm_mask) int i; uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
+ pci_write_config8(PCI_DEV(0,0,0), 0x8e, 0xb0); + for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
uint8_t socket_mask = 1 << i; @@ -1727,7 +1761,7 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) static void ram_set_rcomp_regs(void) { uint32_t dword; - uint8_t maybe_strength_control; + uint8_t maybe_strength_control, revision;
RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
@@ -1745,81 +1779,105 @@ static void ram_set_rcomp_regs(void) write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
/* Begin to write the RCOMP registers */ + write8(RCOMP_MMIO + 0x2c, 0x0);
// Set CMD and DQ/DQS strength to 2x (?) maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88; - maybe_strength_control |= 0x44; + maybe_strength_control |= 0x40; write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80); write16(RCOMP_MMIO + 0x42, 0);
- write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60); - - // NOTE: some factory BIOS set 0x9088 here. Seems to work either way. + // Set CMD and DQ/DQS strength to 2x (?) + maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0xF8; + maybe_strength_control |= 0x04; + write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); + write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x60); write16(RCOMP_MMIO + 0x40, 0);
// Set RCVEnOut# strength to 2x (?) maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8; - maybe_strength_control |= 4; + maybe_strength_control |= 0x04; write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0); write16(RCOMP_MMIO + 0x50, 0);
// Set CS# strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8; - maybe_strength_control |= 4; + maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x88; + maybe_strength_control |= 0x04; write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140); write16(RCOMP_MMIO + 0x48, 0);
+ // Set CS# strength for x4 SDRAM to 2x (?) + maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x8F; + maybe_strength_control |= 0x40; + write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); + write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x160); + write16(RCOMP_MMIO + 0x4a, 0); + // Set CKE strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8; - maybe_strength_control |= 4; + maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x88; + maybe_strength_control |= 0x04; write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0); write16(RCOMP_MMIO + 0x44, 0);
+ // Set CKE strength for x4 SDRAM to 2x (?) + maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x8F; + maybe_strength_control |= 0x40; + write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); + write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xc0); + write16(RCOMP_MMIO + 0x46, 0); + // Set CK strength for x4 SDRAM to 1x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8; - maybe_strength_control |= 1; + maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x88; + maybe_strength_control |= 0x01; write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); - write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180); write16(RCOMP_MMIO + 0x4c, 0);
- write8(RCOMP_MMIO + 0x2c, 0xff); + // Set CK strength for x4 SDRAM to 1x (?) + maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x8F; + maybe_strength_control |= 0x10; + write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); + write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x1a0); + write16(RCOMP_MMIO + 0x4e, 0);
- // Set the digital filter length to 8 (?) - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
- // NOTE: Some factory BIOS don't do this. - // Doesn't seem to matter either way. - dword &= ~2; + dword = read32(RCOMP_MMIO + 0x400); + dword &= 0x7f7fffff; + write32(RCOMP_MMIO + 0x400, dword);
- dword |= 1; - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); + dword = read32(RCOMP_MMIO + 0x408); + dword &= 0x7f7fffff; + write32(RCOMP_MMIO + 0x408, dword);
- /* Wait 40 usec */ - SLOW_DOWN_IO; + ram_handle_d060_1();
- /* unblock updates */ - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - dword &= ~(1 << 9); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); + dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword &= 0x3fffffff; + pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
- // Force a RCOMP measurement cycle? - dword |= (1 << 8); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - dword &= ~(1 << 8); + revision = pci_read_config8(PCI_DEV(0,0,0), 0x08); + if (revision >= 3) { + dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); + dword &= ~0x100; + write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); + dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); + dword |= 0x500; + write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); + } + dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); + dword &= ~0x203; + dword |= 0x401; write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
/* Wait 40 usec */ SLOW_DOWN_IO;
+ // Clear the RCOMP MMIO base address + pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, 0); /*disable access to the rcomp bar */ dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); dword &= ~(1 << 22); @@ -2004,4 +2062,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
ram_set_rcomp_regs(); ram_set_d0f0_regs(); + ram_handle_d060_2(); } +