On Sat, Mar 6, 2010 at 2:01 PM, ron minnich rminnich@gmail.com wrote:
This activity is really impressive. It got me to wondering: how old is the 440bx chipset? I know it's been around a while. It sure seems to live one ...
ron
Yup, 440BX is alive and well. :-)
I got scored by romcc again in the battle to complete its support.
Attached is my working copy of src/northbridge/intel/i440bx/raminit.c with more or less complete SDRAM support at 100MHz. There is one problem: romcc segfaults on it. Because of this, it is not patch ready. It compiles fine on gcc for my test jig. Anything I added to make it compile for my jig did not cause this, as I removed them all and it still segfaults.
Any help is again appreciated.
There is also preliminary work done to combine
sdram_set_registers(); sdram_set_spd_registers(); sdram_enable();
into sdram_initialize(), like i82830. I also added a parameter to it for the motherboard's FSB, so the motherboard romstage can get the FSB off the clock chip and pass it to raminit.c where SDRAM timings are programmed.
I ended up just dumping the configuration space with three 256MB PC133 DIMMs installed in all kind of combinations and analyze that. I tested this code by comparing its output through my test jig with my collected dumps. SerialICE still not involved. :-)
Joseph, the code to initialize the DIMMs are already there before I came onboard. Instead of sending the sequence to one row at a time, the 440BX code sends one command to all populated DIMM rows together. I figure we could save some execution time as this method is not unlike boiling 8 eggs all at once.
By the way where in the source tree would one put code to initialize non-DRAM related aspects of northbridge?
Thanks Keith