Hi Alex, all,
Am 30.03.19 um 02:40 schrieb Alex Feinman:
DDR RComp calculation is explained in the CPU platform design guide. If you are an Intel licensee, you can request this document by number - 561280 for KBL. There seems to be also a whitepaper you can ask your OEM rep for.
that mention of a whitepaper made me search intel.com again. And... finally! I found something. For all with cNDA access: 573387 It's a few slides that explain at least when we have to fill which fields, and a spreadsheet that gives all the numbers (even convenient "computation" of the DQ map stuff for LPDDR). I have no idea why they didn't make that part of FSP, the interface could be so much simpler.
The actual values are calculated based on memory topology and board layout and then fine-tuned through measurement. Basically, if you are a system designer, you have the documents and know how to do it, and if you are not, then these values are calculated by the manufacturer/BIOS writer so your only recourse is to find out from them.
I highly doubt that now. All numbers in coreboot match those in Intel's spreadsheet. So they don't seem to be board specific but only SKU and memory configuration specific (e.g. memory-down vs DIMMs). Even if Intel leaves room for tuning, nobody seems to make use of it.
Well, at least Intel seems to have realized by now that this makes FSP configuration unnecessarily complex: The CNL FSP seems to come with default values (for the Rcomp settings).
I guess, I'll try to get the data from that spreadsheet published. With those tables we can derive all the settings from other information and wouldn't have to set them per board.
Nico
PS. Haha, I've searched for years for this info :D