Hi,
it seems that rs690_htinit() does nothing (it only prints some data). Is that intentional?
The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. I think we could add code for this to rs690_htinit().
/***************************************** * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ static void rs690_htinit() { /* * About HT, it has been done in enumerate_ht_chain(). */ device_t k8_f0; u32 reg; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); /************************ * get k8's ht freq, in k8's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero * value to this reg, and that value takes effect on the next warm reset or * LDTSTOP_L disconnect sequence. * 0000b = 200Mhz * 0010b = 400Mhz * 0100b = 600Mhz * 0101b = 800Mhz * 0110b = 1Ghz * 1111b = 1Ghz ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); }
As you can see, we only read the K8 HT speed.
I have created a patch which tests if the K8 HT speed is 1 GHz and sets NB_CFG_Q_F1000_800 bit 0 in that case.
But this can fail if the processor has more than one HT link. My idea was to look at RS690 HT link configuration instead because it has only one HT link. There is another problem because rs690_htinit() is called before optimize_link_incoherent_ht(). The new link speed is only known after optimize_link_incoherent_ht(). Calling rs690_htinit() too early has no effect.
I call rs690_htinit() again after optimize_link_incoherent_ht().
What do you think?
Regards, Carl-Daniel
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Arbeitskopie) @@ -175,8 +175,9 @@ /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); @@ -196,6 +197,16 @@ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + if ((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) { + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_info("rs690_ht_init NB_CFG_Q_F1000_800=%x\n", reg8); + if (!(reg8 & 0x1)) { + printk_info("rs690_ht_init setting bit 0 in NB_CFG_Q_F1000_800 to allow 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } + } }
/******************************************************* Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie) @@ -210,6 +210,7 @@
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset);