Ronald G. Minnich (rminnich@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2224
-gerrit
commit 44c7efade1af8fcd677f5e2065d8773cb2a2e900 Author: Ronald G. Minnich rminnich@gmail.com Date: Tue Jan 29 14:35:35 2013 -0800
Exynos5250: Get DDR3 working by changing what is compiled and add a function
This is a minor set of changes to get DDR3 going.
Move compilation of DDR3 startup to the romstage. Fix a prototype that was missing a void. Remove a function that is overly flexible, and even though it is overly flexible only actually can handle one type of RAM. Mainboards only support one type of DRAM, so create a function to explicitly initialize the type of DDR we have -- DDR3.
With these changes, and the previous changes, google snow is ready to run the ramstage.
Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5 Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- src/cpu/samsung/exynos5250/Makefile.inc | 4 ++-- src/cpu/samsung/exynos5250/clock_init.c | 2 +- src/cpu/samsung/exynos5250/dmc_common.c | 21 ++------------------- src/cpu/samsung/exynos5250/setup.h | 4 +--- 4 files changed, 6 insertions(+), 25 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 1b915a3..992edce 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,6 +11,8 @@ romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c romstage-y += uart.c +romstage-$(CONFIG_SPL_BUILD) += dmc_common.c +romstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c
#ramstage-y += clock.c #ramstage-y += clock_init.c @@ -30,8 +32,6 @@ ramstage-y += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c -ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c -ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c
exynos5250_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5250 BL1\n" diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index ea91bb4..565abe1 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -744,7 +744,7 @@ struct mem_timings *clock_get_mem_timings(void) return NULL; }
-void system_clock_init() +void system_clock_init(void) { struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_mct_regs *mct_regs = diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c index 35a13ac..f91cbb3 100644 --- a/src/cpu/samsung/exynos5250/dmc_common.c +++ b/src/cpu/samsung/exynos5250/dmc_common.c @@ -26,6 +26,8 @@ #include <common.h> #include <console/console.h> #include <cpu/samsung/exynos5250/setup.h> +#include <cpu/samsung/exynos5250/dmc.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5-common/spl.h> #include <system.h>
@@ -179,22 +181,3 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); }
-void mem_ctrl_init() -{ - struct spl_machine_param *param = spl_get_machine_params(); - struct mem_timings *mem; - int ret; - - mem = clock_get_mem_timings(); - - /* If there are any other memory variant, add their init call below */ - if (param->mem_type == DDR_MODE_DDR3) { - ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %u", ret); - BUG(); - } - } else { - die("Unknown memory type"); - } -} diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index bb438c5..13a46c2 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -706,9 +706,7 @@ void mem_ctrl_init(void); */ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
-/* FIXME(dhendrix): why is this here? commenting it out and we'll use - clock_init.h instead */ -//void system_clock_init(void); +void ddr3_init(void);
void tzpc_init(void); /*