Author: uwe Date: 2008-08-04 17:40:45 +0200 (Mon, 04 Aug 2008) New Revision: 3469
Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c trunk/coreboot-v2/targets/asi/mb_5blgp/ trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb Log: Initial support for the ASI MB-5BLGP (Neoware Eon 4000s).
This works fine in Linux if you use the 'irqpoll' kernel command line option.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb 2008-08-04 15:40:45 UTC (rev 3469) @@ -0,0 +1,137 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +dir /pc80 +config chip.h + +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 0f.0 on end # Ethernet + device pci 12.0 on # ISA bridge + chip superio/nsc/pc87351 # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.e on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # System wake-up control (SWC) + irq 0x60 = 0x500 + end + device pnp 2e.5 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 on # GPIO + irq 0x60 = 0x800 + end + device pnp 2e.8 on # Fan speed control + irq 0x60 = 0x900 + end + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA + device pci 13.0 on end # USB + register "ide0_enable" = "1" + register "ide1_enable" = "0" # No connector on this board + end + end + chip cpu/amd/model_gx1 # CPU + end +end
Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2008-08-04 15:40:45 UTC (rev 3469) @@ -0,0 +1,105 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_VIDEO_MB +uses CONFIG_SPLASH_GRAPHIC +uses CONFIG_GX1_VIDEO +uses CONFIG_GX1_VIDEOMODE +uses PIRQ_ROUTE + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +default CONFIG_GX1_VIDEO = 1 +default CONFIG_GX1_VIDEOMODE = 0 +default CONFIG_SPLASH_GRAPHIC = 1 +default CONFIG_VIDEO_MB = 2 + +default ROM_SIZE = 256 * 1024 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default PIRQ_ROUTE = 1 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_OPTION_TABLE = 0 +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc " +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 + +end
Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c 2008-08-04 15:40:45 UTC (rev 3469) @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/gx1/raminit.c" +#include "cpu/x86/bist.h" +#include "superio/nsc/pc87351/pc87351_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) + +static void main(unsigned long bist) +{ + pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + sdram_init(); + /* ram_check(0, 640 * 1024); */ +}
Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h 2008-08-04 15:40:45 UTC (rev 3469) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_asi_mb_5blgp_ops; +struct mainboard_asi_mb_5blgp_config {};
Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c 2008-08-04 15:40:45 UTC (rev 3469) @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x12 << 3) | 0x0, /* Interrupt router device */ + 0x8800, /* IRQs devoted exclusively to PCI usage */ + 0x1078, /* Vendor */ + 0x2, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x96, /* Checksum */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */ + {0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */ + {0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +}
Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c 2008-08-04 15:40:45 UTC (rev 3469) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_asi_mb_5blgp_ops = { + CHIP_NAME("ASI MB-5BLGP Mainboard") +};
Added: trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb 2008-08-04 15:40:45 UTC (rev 3469) @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target mb_5blgp +mainboard asi/mb_5blgp + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "ASI" +option MAINBOARD_PART_NUMBER = "MB-5BLGP" + +option IRQ_SLOT_COUNT = 3 + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +option CONFIG_GX1_VIDEO = 1 +option CONFIG_GX1_VIDEOMODE = 0 +option CONFIG_SPLASH_GRAPHIC = 1 +option CONFIG_VIDEO_MB = 2 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option COREBOOT_EXTRA_VERSION = ".0Normal" + payload ../payload.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option COREBOOT_EXTRA_VERSION = ".0Fallback" + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"