Re: [coreboot] [PATCH 6/6] Intel EP80579 Development Board mainboard

[Ed Swierk]

At long last, here is a new version of the code for the EP80579
development mainboard (codename Truxton). It has been tested on real
hardware, booting a Linux kernel payload and running memtest86+ with
no errors. This is the final part of the EP80579 (Tolapai) patch set.

I tried to address all your comments from the first version; see
inline for exceptions.

Signed-off-by: Ed Swierk

On Mon, Aug 25, 2008 at 1:49 PM, Uwe Hermann  wrote:
> Comments below, but this should be the last commit anyway (after all the
> NB/SB code is committed; I'll try to review that ASAP).
>
> On Wed, Aug 20, 2008 at 09:19:35AM -0700, Ed Swierk wrote:
> > Index: coreboot-v2-3363/src/mainboard/intel/truxton/Config.lb
> >
> > --- /dev/null
>
> [...]
> > +chip northbridge/intel/i3100
> >    device pci_domain 0 on
> >            device pci 00.0 on end # IMCH
> >            device pci 00.1 on end # IMCH error status
> >            device pci 01.0 on end # IMCH EDMA engine
> >            device pci 02.0 on end # PCIe port A/A0
> >            device pci 03.0 on end # PCIe port A1
> >            device pci 04.0 on end
> >            device pci 08.0 off end
> >            device pci 0d.0 off end
> >            device pci 0d.1 off end
>
> What are these? Please add comments. Why are three of them disabled?
> Not available on this board?

I don't know what these are, but I found that the latter three have to
be set to "off", else the PCI bus setup hangs.
> >                    device pci 1f.2 on end  # SATA
> >                    device pci 1f.3 on end  # SMBus
> >                    device pci 1f.4 on end
>
> Same here.

I don't know what this is, either, and the datasheet doesn't say. But
I figured since this is a development board there's no harm in leaving
it on. Perhaps someone else will figure out that it's a built-in MP3
player or something.
> >            end
> >    end
> >    device apic_cluster 0 on
> >            chip cpu/intel/ep80579
> >                    device apic 0 on end
> >            end
> >    end
> >
> > +end
> > Index: coreboot-v2-3363/src/mainboard/intel/truxton/irq_tables.c
> >
> > --- /dev/null
> > +++ coreboot-v2-3363/src/mainboard/intel/truxton/irq_tables.c
> > @@ -0,0 +1,44 @@
> > +/*
> > This file is part of the coreboot project.
> > Copyright (C) 2008 Arastra, Inc.
> > This program is free software; you can redistribute it and/or modify
> > it under the terms of the GNU General Public License version 2 as
> > published by the Free Software Foundation.
> > This program is distributed in the hope that it will be useful,
> > but WITHOUT ANY WARRANTY; without even the implied warranty of
> > MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > GNU General Public License for more details.
> > You should have received a copy of the GNU General Public License
> > along with this program; if not, write to the Free Software
> > Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> > */
> >
> > +#include <arch/pirq_routing.h>
> >
> > +const struct irq_routing_table intel_irq_routing_table = {
> > PIRQ_SIGNATURE, /* u32 signature */
> > PIRQ_VERSION,   /* u16 version   */
> > 32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
> > 0x00,       /* u8 Bus 0 */
> > (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
> > 0x0000,     /* u16 reserve IRQ for PCI */
> > 0x8086,     /* u16 Vendor */
> > 0x5031,     /* Device ID */
> > 0x00000000, /* u32 miniport_data */
> > { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
> > 0x5e,   /*  u8 checksum - mod 256 checksum must give zero */
> > {  /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
> >     {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
>
> Please add a coment what device/slot this is.

I have no idea--my understanding of the IRQ routing business is pretty
fuzzy. But Linux wasn't happy booting without it, if I recall.

--Ed