Re: [LinuxBIOS] linuxbios Digest, Vol 25, Issue 79

[C.-Valentin Schmitt]

looks like symbiotic bios - stuff . . .

my recommendation: $hithappen$
> -----Ursprüngliche Nachricht-----
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> Gesendet: 20.03.07 12:15:48
> An: [e-mail]
> Betreff: linuxbios Digest, Vol 25, Issue 79
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> Today's Topics:
> Re: how flashrom works (Stefan Reinauer)
> Re: usage of pci_write_config32()? (Corey Osgood)
> Re: linuxbios Digest, Vol 25, Issue 71 (C.-Valentin Schmitt)
> microcode updates on amd64 (Stefan Reinauer)
>
> Message: 1
> Date: Tue, 20 Mar 2007 09:52:16 +0100
> From: Stefan Reinauer 
> Subject: Re: [LinuxBIOS] how flashrom works
> To: Anton 
> Cc: [e-mail]
> Message-ID: 
> Content-Type: text/plain; charset=utf-8
> Anton  [070320 09:31]:
> > Can someone give me a pointer on flashrom programming?
> >    I look into sst28sf040.h, there are 3 functions available: probe(),
> > erase(), write(). How the read() from chip is implemented?
>
> The area is mmap'ed and then just read as normal memory. 
> If you do -r, it uses memcpy, flash_rom.c:325
>
> Stefan
>
> Message: 2
> Date: Tue, 20 Mar 2007 05:30:25 -0400
> From: Corey Osgood 
> Subject: Re: [LinuxBIOS] usage of pci_write_config32()?
> To: Stefan Reinauer 
> Cc: ron minnich ,	LinuxBIOS Mailing List
>    
> Message-ID: 
> Content-Type: text/plain; charset=UTF-8
>
> Stefan Reinauer wrote:
> > Corey Osgood  [070320 05:45]:
> > > It's raminit.c from LBv1's src/northbridge/440gx/, it addresses the
> > > first register for a 32-bit write to 0x50-0x53, then the second for a
> > > 16-bit write later on, can't see at the moment which it was. I'm working
> > > on trying to port that up to v2, to see if it'll work on a 440zx, since
> > > nothing else I've done seems to be working.
> >
> > Note that on some systems, a 32bit write is very different from 4 8bit
> > writes. If it is a 32bit register, you should always read/write all 32
> > bits.
> >
> > Stefan
>
> Yes, but on 440bx doesn't seem to matter, LBv1 uses 8-bit writes all
> over the place on it. And yes, it was 0x44332211, written to the last
> reg in the set, I've fixed my code accordingly (not that it works, but
> at least correct now on that part).
>
> -Corey
>
> Message: 3
> Date: Tue, 20 Mar 2007 10:56:41 +0100
> From: "C.-Valentin Schmitt" 
> Subject: Re: [LinuxBIOS] linuxbios Digest, Vol 25, Issue 71
> To: [e-mail]
> Message-ID: 
> Content-Type: text/plain; charset=iso-8859-15
>
> I dont know ! I have no clue !
>
> misco ???
> kingston ???
> > -----Urspr?ngliche Nachricht-----
> > Von: [e-mail]
> > Gesendet: 19.03.07 09:47:00
> > An: [e-mail]
> > Betreff: linuxbios Digest, Vol 25, Issue 71
> > Send linuxbios mailing list submissions to
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> > than "Re: Contents of linuxbios digest..."
> >
> > Today's Topics:
> > Re: Flashrom and AM29LV040B flash chip (Peter Stuge)
> > Re: filo ide speedup patch? (Peter Stuge)
> > Re: linuxbios + xf86-video-unichrome: no VGA BIOS	needed.
> > (Peter Stuge)
> > Re: filo ide speedup patch? (Peter Stuge)
> > Getting Friendly with Flashrom (David H. Barr)
> > Re: Getting Friendly with Flashrom (Peter Stuge)
> > Re: Is my hardware supported? (Corey Osgood)
> > Re: northbridge docs ([e-mail])
> > Re: northbridge docs (Corey Osgood)
> >
> > Message: 1
> > Date: Mon, 19 Mar 2007 01:08:37 +0100
> > From: Peter Stuge 
> > Subject: Re: [LinuxBIOS] Flashrom and AM29LV040B flash chip
> > To: [e-mail]
> > Message-ID: 
> > Content-Type: text/plain; charset=us-ascii
> >
> > On Sun, Mar 18, 2007 at 05:46:34PM +0200, Priit Laes wrote:
> > > How well does Flashrom work with AM29LV040B [1] flash chip?
> >
> > It should work out of the box, if not it will be trivial to add.
> > > I took apart my old Dell Latitude C600 laptop with thoughts that I could
> > > maybe get it working with LinuxBIOS, but well, chip itself is soldered
> > > on the motherboard [2] (16 pins inside 8 millimeters) so I would first
> > > have to figure out how to implement the hotswapping.
> >
> > Emulation Technology have a TSOP prototyping socket that you could
> > solder on to the board instead of the TSOP chip. Then have a few TSOP
> > chips to swap between.
> >
> > http://www.emulation.com/catalog/off-the-shelf_solutions/sockets/tsop/
> >
> > Note that these sockets are rated for a minimum of 50 insert/remove
> > cycles.
> > > Also, does anyone have ideas where to order these flash chips
> > > (PLCC) in Europe, preferably Finland?
> >
> > On the picture is a TSOP chip. Either way, I think Farnell or maybe
> > Avnet are good sources for single quantity chips.
> > > [2] http://plaes.org/files/2007-Q1/2007-03-18-latitude-c600-bios.jpg
> >
> > There are pads for a PLCC chip on the board. PLCC is much easier to
> > work with so I would go for that instead of the TSOP. (Maybe that was
> > your thought too.) You would have to scrape off the green lacquer to
> > expose the pads but if done carefully with a steady hand and a sharp
> > knife (or fibre glass brush) that's fairly easy.
> >
> > //Peter
> >
> > Message: 2
> > Date: Mon, 19 Mar 2007 01:20:53 +0100
> > From: Peter Stuge 
> > Subject: Re: [LinuxBIOS] filo ide speedup patch?
> > To: [e-mail]
> > Message-ID: 
> > Content-Type: text/plain; charset="us-ascii"
> >
> > On Sun, Mar 18, 2007 at 06:36:44PM +0100, Stefan Reinauer wrote:
> > > > Find attached a patch for timer2 and hard reset. I'm looking at
> > > > FILO right now.
> > >
> > > The below patch works fine on my system, but some older versions of
> > > the C3 lack support for the rdtsc command. (Nehemiah has it)
> > >
> > > Whereas the Centaur/Wincore is said to not have rdtsc.
> >
> > Aha!
> > > I would assume the patch is wrong for the epia and right for the
> > > epia-m.
> > >
> > > Do you mind dropping the epia part?
> >
> > Not at all, we should have working defaults, but I'll add a note to
> > the wiki for people to enable it if they have Nehemiah.
> >
> > Can CONFIG_UDELAY_TSC=1 in targets/via/epia/Config.lb also
> > automatically set CONFIG_UDELAY_IO=0 ?
> >
> > //Peter