On Wed, Jul 25, 2007 at 07:09:42PM -0400, john wrote:
- Kernel loading is slow but initrd loading is very, very, slow.
Please try the FILO patch in this message:
http://www.linuxbios.org/pipermail/linuxbios/2007-May/021586.html
You don't have to enable the DEBUG_* values but if the patched FILO doesn't work properly I would appreciate if you could send the output of a version built with the DEBUG_ values enabled.
You should see a bit of improvement with it applied.
Now, VGA:
Allocating VGA resource PCI: 07:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0f.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] io <node 0 link 0> PCI: 00:18.0 1b8 <- [0x00e0000000 - 0x00efffffff] prefmem <node 0 link 0> PCI: 00:18.0 1b0 <- [0x00f4000000 - 0x00f71fffff] mem <node 0 link 0> PCI: 00:01.0 14 <- [0x00f7144000 - 0x00f7144fff] mem
[..]
PCI: 07:00.0 10 <- [0x00f6000000 - 0x00f6ffffff] mem PCI: 07:00.0 14 <- [0x00e0000000 - 0x00efffffff] prefmem64 PCI: 07:00.0 1c <- [0x00f4000000 - 0x00f5ffffff] mem64 PCI: 07:00.0 24 <- [0x0000001000 - 0x000000107f] io PCI: 07:00.0 30 <- [0x00f7000000 - 0x00f701ffff] romem PCI: 00:18.3 94 <- [0x00f0000000 - 0x00f3ffffff] mem <gart>
[..]
rom address for PCI: 07:00.0 = f7000000 copying VGA ROM Image from 0xf7000000 to 0xc0000, 0xda00 bytes entering emulator halt_sys: file /home/selmys/seneca/072/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c, line 4387
This says that the VGA BIOS ran OK. Do you always get textmode on the monitor during boot - before you start X?
PCI->APIC IRQ transform: 0000:07:00.0[A] -> IRQ 17
[..]
(II) PCI-to-ISA bridge: (II) Bus -1: bridge is at (0:1:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set)
-1 ?!
(II) PCI-to-PCI bridge: (II) Bus 1: bridge is at (0:6:0), (0,1,1), BCTRL: 0x0a03 (VGA_EN is cleared) (II) PCI-to-PCI bridge: (II) Bus 2: bridge is at (0:10:0), (0,2,2), BCTRL: 0x0003 (VGA_EN is cleared) (II) PCI-to-PCI bridge: (II) Bus 3: bridge is at (0:11:0), (0,3,3), BCTRL: 0x0003 (VGA_EN is cleared) (II) PCI-to-PCI bridge: (II) Bus 4: bridge is at (0:12:0), (0,4,4), BCTRL: 0x0003 (VGA_EN is cleared) (II) PCI-to-PCI bridge: (II) Bus 5: bridge is at (0:13:0), (0,5,5), BCTRL: 0x0003 (VGA_EN is cleared) (II) PCI-to-PCI bridge: (II) Bus 6: bridge is at (0:14:0), (0,6,6), BCTRL: 0x0003 (VGA_EN is cleared) (II) PCI-to-PCI bridge: (II) Bus 7: bridge is at (0:15:0), (0,7,7), BCTRL: 0x000b (VGA_EN is set)
Oops. X thinks the bridge is at 0:15, while LB likes 0:18.
(II) Bus 7 I/O range: [0] -1 0 0x00001000 - 0x00001fff (0x1000) IX[B]
This isn't right, LB only sets 0x80 ports.
(II) Bus 7 non-prefetchable memory range: [0] -1 0 0xf4000000 - 0xf70fffff (0x3100000) MX[B]
This is mem64+mem+romem as set by LB plus another 0xe0000 bytes.
(II) Bus 7 prefetchable memory range: [0] -1 0 0xe0000000 - 0xefffffff (0x10000000) MX[B]
Same as LB prefmem64.
(II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:24:0), (0,0,7), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x100000000) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x100000000) MX[B] (--) PCI: (0:1:3) nVidia Corporation MCP55 SMU rev 162, Mem @ 0xf7100000/18 (--) PCI:*(7:0:0) nVidia Corporation unknown chipset (0x0400) rev 161, Mem @ 0xf6000000/24, 0xe0000000/28, 0xf4000000/25, I/O @ 0x1000/7, BIOS @ 0xf7000000/17
This has the resources correct, but I wonder about the parent bus difference above..
[..]
(WW) NVIDIA: No matching Device section for instance (BusID PCI:0:1:3) found (--) Assigning device section with no busID to primary device (--) Chipset NVIDIA GPU found
Why does X mention 0:1:3 (the MCP55) as a candidate here?
//Peter