[coreboot] Re: denverton: crash when using coreboot 4.17

[Arthur Heymans]

Hi

Can you try selecting "NO_FSP_TEMP_RAM_EXIT" in the denverton_ns Kconfig?
That way coreboot uses native code to tear down CAR (so without FSP
TempRamExit)
INTEL_CAR_NEM_ENHANCED also needs to be select in the FSP_CAR option for
that to work (so it knows how to tear down CAR).

Kind regards
Arthur

On Mon, Jun 13, 2022 at 4:46 PM Sumo  wrote:
> Hi,
>
> Update: I found the bad commit:
>
> commit 5315e96abfa5b45fcd53149df5ebaa069a830558
> Author: Arthur Heymans 
> Date:   Fri May 14 11:22:31 2021 +0200
> arch/x86/postcar: Use a separate stack for C execution
>
> Add a stack in .bss for C execution. This will make it easier to move
> the setup of MTRRs in C code.
>
> Hehehe, this confirmed my suspicion that the problem was in the
> POSTCAR...should have done a grep for postcar in git log instead of the
> painful bisect :D
>
> So denverton_ns is broken due to this commit, how can we proceed? I guess
> a git revert is not an option right, since this change looks like a base
> for future implementations... Please let me know if you need more tests.
>
> Kind regards,
> Sumo
>
> On Mon, Jun 13, 2022 at 9:37 AM Sumo  wrote:
> > Thanks Paul, I'll try bisect.
> >
> > Do we have any instructions of how to use the normal/fallback coreboot
> > stage prefixes? During the bisect it will be painful always bricking the
> > board and having to use a flash programmer for restoring instead of using
> > flashrom.
> >
> > Should I build setting BOOTBLOCK_NORMAL + normal prefix, and then reuse a
> > prebuilt coreboot.rom with fallback stages included? Anything else needed
> > besides having a cmos layout?
> >
> > Kind regards,
> > Sumo
> >
> > On Sat, Jun 11, 2022 at 3:15 AM Paul Menzel 
> > wrote:
> > > Dear Suma,
> > >
> > > Am 11.06.22 um 00:16 schrieb Sumo:
> > > > My denverton system is crashing after the FSM memory init, probably
> > >
> > > when
> > > > jumping to POSTCAR. The following lines are shown before the crash:
> > > >
> > > > [DEBUG]  TPM: Digest of `CBFS: fallback/postcar` to PCR 2 logged
> > > > [DEBUG]  Loading module at 0x7f7ce000 with entry 0x7f7ce031. filesize:
> > > > 0x6060 memsize: 0xc358
> > > > [DEBUG]  Processing 246 relocs. Offset value of 0x7d7ce000
> > > > [DEBUG]  BS: romstage times (exec / console): total (unknown) / 1350 ms
> > > >
> > > > Below are my CAR settings:
> > > > # CONFIG_USE_DENVERTON_NS_CAR_NEM_ENHANCED is not set
> > > > CONFIG_USE_DENVERTON_NS_FSP_CAR=y
> > > > CONFIG_ARCH_POSTCAR_X86_32=y
> > > > CONFIG_POSTCAR_STAGE=y
> > > > CONFIG_CARDBUS_PLUGIN_SUPPORT=y
> > > > CONFIG_FSP_CAR=y
> > > > CONFIG_POSTCAR_CONSOLE=y
> > > >
> > > > Everything is fine when using coreboot v4.14.
> > > >
> > > > I have tried using CONFIG_USE_DENVERTON_NS_CAR_NEM_ENHANCED but things
> > >
> > > got
> > > > even worse - in this case nothing is shown in the console output.
> > > >
> > > > Any suggestions?
> > >
> > > It’d be great if you could bisect.
> > >
> > > Kind regards,
> > >
> > > Paul
> > >
> > > PS: In your address book please spell coreboot lowercase. ;-)
>
> coreboot mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]