Sebastian Andrzej Siewior (sebastian@breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1631
-gerrit
commit 84f9417cb9512e2bb965726dccafc254d9fee57b Author: Sebastian Andrzej Siewior bigeasy@linutronix.de Date: Fri Oct 26 19:02:44 2012 +0200
iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
The PCI registers should be accessed aligned and 0x62 is not 32bit aligned therefore this patch changes it to a 16bit access.
Change-Id: I00725a4569f471eedb061834f626911b42e734fb Signed-off-by: Sebastian Andrzej Siewior bigeasy@linutronix.de --- src/mainboard/iwave/iWRainbowG6/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 833d930..02bd1a5 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -324,8 +324,8 @@ static void poulsbo_setup_Stage2Regs(void) u32 reg32;
printk(BIOS_DEBUG, "Reserved"); - reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62); - pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3)); + reg32 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62); + pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3)); /* Slot capabilities */ pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500); pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);