Author: rminnich Date: 2008-08-01 19:03:22 +0200 (Fri, 01 Aug 2008) New Revision: 702
Added: coreboot-v3/arch/x86/amd/ coreboot-v3/arch/x86/amd/stage0.S coreboot-v3/arch/x86/amdk8/ coreboot-v3/arch/x86/amdk8/stage1.c coreboot-v3/arch/x86/intel/ coreboot-v3/include/arch/x86/amd_k8.h coreboot-v3/include/arch/x86/mtrr.h coreboot-v3/mainboard/gigabyte/ coreboot-v3/mainboard/gigabyte/Kconfig coreboot-v3/mainboard/gigabyte/m57sli/ coreboot-v3/mainboard/gigabyte/m57sli/Kconfig coreboot-v3/mainboard/gigabyte/m57sli/Makefile coreboot-v3/mainboard/gigabyte/m57sli/dts coreboot-v3/mainboard/gigabyte/m57sli/initram.c coreboot-v3/mainboard/gigabyte/m57sli/stage1.c Removed: coreboot-v3/arch/x86/mtrr.h Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/Makefile coreboot-v3/mainboard/Kconfig Log: The m57sli almost builds. It's pretty empty. The dtc is not run .
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Marc Jones marc.jones@amd.com
Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-08-01 16:59:09 UTC (rev 701) +++ coreboot-v3/arch/x86/Kconfig 2008-08-01 17:03:22 UTC (rev 702) @@ -48,6 +48,14 @@ arch/x86/Makefile for more hints on possible values. It is usually set in mainboard/*/Kconfig.
+config CPU_AMD_K8 + boolean + help + CPU type. At the moment this option selects the reset vector and + Cache-as-RAM (CAR) implementation for a mainboard. See + arch/x86/Makefile for more hints on possible values. + It is usually set in mainboard/*/Kconfig. + config OPTION_TABLE boolean help @@ -74,6 +82,7 @@ hex default 0x8f000 if CPU_I586 default 0x80000 if CPU_AMD_GEODELX + default 0xc8000 if CPU_AMD_K8 help This option sets the base address of the area used for CAR.
@@ -81,5 +90,6 @@ hex default 0x1000 if CPU_I586 default 0x8000 if CPU_AMD_GEODELX + default 0x08000 if CPU_AMD_K8 help This option sets the size of the area used for CAR.
Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-08-01 16:59:09 UTC (rev 701) +++ coreboot-v3/arch/x86/Makefile 2008-08-01 17:03:22 UTC (rev 702) @@ -124,9 +124,12 @@ STAGE0_ARCH_X86_OBJ += geodelx/stage1.o STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o else - STAGE0_CAR_OBJ = stage0_i586.o +ifeq ($(CONFIG_CPU_AMD_K8),y) + STAGE0_CAR_OBJ = amd/stage0.o + STAGE0_ARCH_X86_OBJ += amdk8/stage1.o endif endif +endif
ifeq ($(CONFIG_PAYLOAD_NO_PREPARSE_ELF), y) PARSEELF = @@ -245,6 +248,15 @@ $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
+$(obj)/arch/x86/amd/stage0.o: $(src)/arch/x86/amd/stage0.S + $(Q)mkdir -p $(dir $@) + $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) -E $(COREBOOTINCLUDE) $< \ + -o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \ + -DRESRVED=0xf0 -DDATE="`date +%Y/%m/%d`" + $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@ + $(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ) $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
Added: coreboot-v3/arch/x86/amd/stage0.S =================================================================== --- coreboot-v3/arch/x86/amd/stage0.S (rev 0) +++ coreboot-v3/arch/x86/amd/stage0.S 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,467 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include "../macros.h" +#define CacheSize DCACHE_RAM_SIZE +#define CacheBase DCACHE_RAM_BASE +#define MEM_TOPK 2048 +#define ASSEMBLY + +/* leave some space for global variable to pass to RAM stage */ +#define GlobalVarSize 32 + +#ifdef CONFIG_CPU_AMD_K10 +#define CacheSizeAPStack 0x400 /* 1K */ +#endif + +#include <mtrr.h> +#include <amd_k8.h> + + .code16 + .globl _stage0 +_stage0: + cli + + /* Save the BIST result. */ + movl %eax, %ebp; + + /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before + * executing any further code. Even though paging is disabled we + * could still get false address translations due to the TLB if we + * didn't invalidate it. + */ + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB. */ + + /* Switch to protected mode. */ + + /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) + * using BFD version 2.15.94.0.2.2 20041220 this works fine without + * all the ld hackery and so on. So leave it as is with this comment. + */ + + data32 lgdt %cs:gdtptr + + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 + + /* Restore BIST result. */ + movl %ebp, %eax + + // port80_post(0x23) + + /* Now we are in protected mode. Jump to a 32 bit code segment. */ + data32 ljmp $ROM_CODE_SEG, $protected_stage0 + + /* I am leaving this weird jump in here in the event that future gas + * bugs force it to be used. + */ + /* .byte 0x66 */ + .code32 + /* ljmp $ROM_CODE_SEG, $protected_stage0 */ + + /* .code16 */ + .align 4 + .globl gdt16 +gdt16 = . - _stage0 +gdt16x: + .word gdt16xend - gdt16x -1 /* Compute the table limit. */ + .long gdt16x + .word 0 + + /* selgdt 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 +gdt16xend: + + /* From now on we are 32bit. */ + .code32 + + /* We have two gdts where we could have one. That is ok. + * + * Let's not worry about this -- optimizing gdt is pointless since + * we're only in it for a little bit. + * + * Btw. note the trick below: The GDT points to ITSELF, and the first + * good descriptor is at offset 8. So you word-align the table, and + * then because you chose 8, you get a nice 64-bit aligned GDT entry, + * which is good as this is the size of the entry. + * + * Just in case you ever wonder why people do this. + */ + .align 4 + .globl gdtptr + .globl gdt_limit +gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ + +gdt: +gdtptr: + .word gdt_end - gdt -1 /* Compute the table limit. */ + .long gdt /* We know the offset. */ + .word 0 + + /* selgdt 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + + /* selgdt 0x18, flat code segment for CAR */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x20, flat data segment for CAR */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 +gdt_end: + + /* When we come here we are in protected mode. We expand the stack + * and copy the data segment from ROM to the memory. + * + * After that, we call the chipset bootstrap routine that + * does what is left of the chipset initialization. + * + * Note: Aligned to 4 so that we are sure that the prefetch + * cache will be reloaded. + */ + + .align 4 + .globl protected_stage0 +protected_stage0: + /* This code was used by v2. TODO. */ + lgdt %cs:gdtptr + ljmp $ROM_CODE_SEG, $__protected_stage0 + +.globl __protected_stage0 +__protected_stage0: + /* Save the BIST result */ + movl %eax, %ebp + + /*for normal part %ebx already contain cpu_init_detected from fallback call */ + +cache_as_ram_setup: + + movb $0xA0, %al + outb %al, $0x80 + + /* check if cpu_init_detected */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(1 << 11), %eax + movl %eax, %ebx /* We store the status */ + +#ifdef CONFIG_CPU_AMD_K10 + /* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */ + + /* Only BSP needed, for other nodes set during HT/memory init. */ + /* So we need to check if it is BSP */ + movl $0x1b, %ecx + rdmsr + bt $8, %eax /*BSC */ + jnc CAR_FAM10_out + + /* Enable RT tables on BSP */ + movl $0x8000c06c, %eax + movw $0xcf8, %dx + outl %eax, %dx + addw $4, %dx + inl %dx, %eax + btr $0, %eax + outl %eax, %dx + + /* Setup temporary DRAM map: [0,16M) bit 0-23 */ + movl $0x8000c144, %eax + movw $0xcf8, %dx + outl %eax, %dx + addw $4, %dx + movl $0, %eax + outl %eax, %dx + + movl $0x8000c140, %eax + movw $0xcf8, %dx + outl %eax, %dx + addw $4, %dx + movl $3, %eax + outl %eax, %dx + +CAR_FAM10_out: + +#endif + +#ifdef CONFIG_CPU_AMD_K10 + /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. + Re-enable it in after RAM is initialized and before CAR is disabled */ + movl $0xc001102a, %ecx + rdmsr + bts $15, %eax + wrmsr +#endif + + /* Set MtrrFixDramModEn for clear fixed mtrr */ +enable_fixed_mtrr_dram_modify: + movl $SYSCFG_MSR, %ecx + rdmsr + andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax + orl $SYSCFG_MSR_MtrrFixDramModEn, %eax + wrmsr + + /* Clear all MTRRs */ + xorl %edx, %edx + movl $fixed_mtrr_msr, %esi + +clear_fixed_var_mtrr: + lodsl (%esi), %eax + testl %eax, %eax + jz clear_fixed_var_mtrr_out + + movl %eax, %ecx + xorl %eax, %eax + wrmsr + + jmp clear_fixed_var_mtrr +clear_fixed_var_mtrr_out: + +/* 0x06 is the WB IO type for a given 4k segment. + * 0x1e is the MEM IO type for a given 4k segment (K10 and above). + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution + * of this macro, %eax and %edx are cleared. Later invocations of this + * macro will have a monotonically increasing segs parameter. + */ + xorl \reg, \reg +#ifdef CONFIG_CPU_AMD_K10 +.elseif \segs == 1 + movl $0x1e000000, \reg /* WB MEM type */ +.elseif \segs == 2 + movl $0x1e1e0000, \reg /* WB MEM type */ +.elseif \segs == 3 + movl $0x1e1e1e00, \reg /* WB MEM type */ +.elseif \segs >= 4 + movl $0x1e1e1e1e, \reg /* WB MEM type */ +#else +.elseif \segs == 1 + movl $0x06000000, \reg /* WB IO type */ +.elseif \segs == 2 + movl $0x06060000, \reg /* WB IO type */ +.elseif \segs == 3 + movl $0x06060600, \reg /* WB IO type */ +.elseif \segs >= 4 + movl $0x06060606, \reg /* WB IO type */ +#endif +.endif +.endm + +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + extractmask gas_bug_workaround, %eax + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + extractmask gas_bug_workaround, %edx +/* Without the gas bug workaround, the entire macro would consist only of the + * two lines below. + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + */ +.endm + +#if CacheSize > 0x10000 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 + /* enable caching for 32K-64K using fixed mtrr */ + movl $0x268, %ecx /* fix4k_c0000*/ + simplemask CacheSize, 0x8000 + wrmsr +#endif + + /* enable caching for 0-32K using fixed mtrr */ + movl $0x269, %ecx /* fix4k_c8000*/ + simplemask CacheSize, 0 + wrmsr + + /* enable memory access for first MBs using top_mem */ + movl $TOP_MEM, %ecx + xorl %edx, %edx + movl $(((MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax + wrmsr + + + /* disable cache */ + movl %cr0, %eax + orl $(1 << 30),%eax + movl %eax, %cr0 +/* this seems safe to do always. Leave it for now. */ +/*#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))*/ + /* Set the default memory type and enable fixed and variable MTRRs */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + /* Enable Variable and Fixed MTRRs */ + movl $0x00000c00, %eax + wrmsr + + /* Enable the MTRRs and IORRs in SYSCFG */ + movl $SYSCFG_MSR, %ecx + rdmsr + orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax + wrmsr + + movb $0xA1, %al + outb %al, $0x80 + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + + +#ifdef CONFIG_CPU_AMD_K10 + /* So we need to check if it is BSP */ + movl $0x1b, %ecx + rdmsr + bt $8, %eax /*BSC */ + jnc CAR_FAM10_ap +#endif + + movb $0xA2, %al + outb %al, $0x80 + +/*#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))*/ + /* Read the range with lodsl*/ + cld + movl $CacheBase, %esi + movl $(CacheSize >> 2), %ecx + rep lodsl + /* Clear the range */ + movl $CacheBase, %edi + movl $(CacheSize >> 2), %ecx + xorl %eax, %eax + rep stosl + +//#endif /*USE_FAILOVER_IMAGE == 1*/ + + /* set up the stack pointer */ + movl $(CacheBase + CacheSize - GlobalVarSize), %eax + movl %eax, %esp + + movb $0xA3, %al + outb %al, $0x80 + +#ifdef CONFIG_CPU_AMD_K10 + + jmp CAR_FAM10_ap_out +CAR_FAM10_ap: + /* need to set stack pointer for AP */ + /* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/ + /* So need to get the NodeID and CoreID at first */ + /* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */ + + /* store our init detected */ + movl %ebx, %esi + + /* get the coreid bits at first */ + movl $0x80000008, %eax + cpuid + shrl $12, %ecx + andl $0x0f, %ecx + movl %ecx, %edi + + /* get the initial apic id */ + movl $1, %eax + cpuid + shrl $24, %ebx + + /* get the nb cfg bit 54 */ + movl $0xc001001f, %ecx /* NB_CFG_MSR */ + rdmsr + movl %edi, %ecx /* CoreID bits */ + bt $(54-32), %edx + jc roll_cfg + rolb %cl, %bl +roll_cfg: + + /* calculate stack pointer */ + movl $CacheSizeAPStack, %eax + mull %ebx + movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp + subl %eax, %esp + + /* retrive init detected */ + movl %esi, %ebx + + movb $0xA4, %al + outb %al, $0x80 + +CAR_FAM10_ap_out: +#endif + + movb $0xA5, %al + outb %al, $0x80 + + /* Restore the BIST result */ + movl %ebp, %eax + + /* We need to set ebp ? No need */ + movl %esp, %ebp + pushl %ebx /* init detected */ + pushl %eax /* bist */ + call stage1_main + /* We will not go back */ + + movb $0xAF, %al /* Should never see this postcode */ + outb %al, $0x80 + +fixed_mtrr_msr: + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F +var_mtrr_msr: + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F +var_iorr_msr: + .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 +mem_top: + .long 0xC001001A, 0xC001001D + .long 0x000 /* NULL, end of table */ + +cache_as_ram_setup_out:
Added: coreboot-v3/arch/x86/amdk8/stage1.c =================================================================== --- coreboot-v3/arch/x86/amdk8/stage1.c (rev 0) +++ coreboot-v3/arch/x86/amdk8/stage1.c 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <msr.h> +#include <amd_k8.h> + +/** + * Disable Cache As RAM (CAR) after memory is setup. + * + * Unknown how to do this just yet. + */ +void disable_car(void) +{ + /* OK, here is the theory: we should be able to copy + * the data back over itself, and the wbinvd should then + * flush to memory. Let's see. + */ + __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); + __asm__ __volatile__ ("wbinvd\n"); + banner(BIOS_DEBUG, "Disable_car: done wbinvd"); + banner(BIOS_DEBUG, "disable_car: done"); +}
Deleted: coreboot-v3/arch/x86/mtrr.h =================================================================== --- coreboot-v3/arch/x86/mtrr.h 2008-08-01 16:59:09 UTC (rev 701) +++ coreboot-v3/arch/x86/mtrr.h 2008-08-01 17:03:22 UTC (rev 702) @@ -1,41 +0,0 @@ -#ifndef ARCH_X86_MTRR_H -#define ARCH_X86_MTRR_H - -/* These are the region types */ -#define MTRR_TYPE_UNCACHEABLE 0 -#define MTRR_TYPE_WRCOMB 1 -/*#define MTRR_TYPE_ 2*/ -/*#define MTRR_TYPE_ 3*/ -#define MTRR_TYPE_WRTHROUGH 4 -#define MTRR_TYPE_WRPROT 5 -#define MTRR_TYPE_WRBACK 6 -#define MTRR_NUM_TYPES 7 - -#define MTRRcap_MSR 0x0fe -#define MTRRdefType_MSR 0x2ff - -#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) -#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) - -#define NUM_FIXED_RANGES 88 -#define MTRRfix64K_00000_MSR 0x250 -#define MTRRfix16K_80000_MSR 0x258 -#define MTRRfix16K_A0000_MSR 0x259 -#define MTRRfix4K_C0000_MSR 0x268 -#define MTRRfix4K_C8000_MSR 0x269 -#define MTRRfix4K_D0000_MSR 0x26a -#define MTRRfix4K_D8000_MSR 0x26b -#define MTRRfix4K_E0000_MSR 0x26c -#define MTRRfix4K_E8000_MSR 0x26d -#define MTRRfix4K_F0000_MSR 0x26e -#define MTRRfix4K_F8000_MSR 0x26f - -#if !defined (ASSEMBLY) - -void x86_setup_var_mtrrs(unsigned address_bits); -void x86_setup_mtrrs(unsigned address_bits); -int x86_mtrr_check(void); - -#endif - -#endif /* ARCH_X86_MTRR_H */
Added: coreboot-v3/include/arch/x86/amd_k8.h =================================================================== --- coreboot-v3/include/arch/x86/amd_k8.h (rev 0) +++ coreboot-v3/include/arch/x86/amd_k8.h 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 + +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 + +#define IORR_FIRST 0xC0010016 +#define IORR_LAST 0xC0010019 + +#define MTRR_READ_MEM (1 << 4) +#define MTRR_WRITE_MEM (1 << 3) + +#define SYSCFG_MSR 0xC0010010 +#define SYSCFG_MSR_TOM2En (1 << 21) +#define SYSCFG_MSR_MtrrVarDramEn (1 << 20) +#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19) +#define SYSCFG_MSR_MtrrFixDramEn (1 << 18) +#define SYSCFG_MSR_UcLockEn (1 << 17) +#define SYSCFG_MSR_ChxToDirtyDis (1 << 16) +#define SYSCFG_MSR_ClVicBlkEn (1 << 11) +#define SYSCFG_MSR_SetDirtyEnO (1 << 10) +#define SYSCFG_MSR_SetDirtyEnS (1 << 9) +#define SYSCFG_MSR_SetDirtyEnE (1 << 8) +#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5)) +#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0)) + +#define IORR0_BASE 0xC0010016 +#define IORR0_MASK 0xC0010017 +#define IORR1_BASE 0xC0010018 +#define IORR1_MASK 0xC0010019 +#define TOP_MEM 0xC001001A +#define TOP_MEM2 0xC001001D + +#define TOP_MEM_MASK 0x007fffff +#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) + +
Copied: coreboot-v3/include/arch/x86/mtrr.h (from rev 699, coreboot-v3/arch/x86/mtrr.h) =================================================================== --- coreboot-v3/include/arch/x86/mtrr.h (rev 0) +++ coreboot-v3/include/arch/x86/mtrr.h 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,41 @@ +#ifndef ARCH_X86_MTRR_H +#define ARCH_X86_MTRR_H + +/* These are the region types */ +#define MTRR_TYPE_UNCACHEABLE 0 +#define MTRR_TYPE_WRCOMB 1 +/*#define MTRR_TYPE_ 2*/ +/*#define MTRR_TYPE_ 3*/ +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 +#define MTRR_NUM_TYPES 7 + +#define MTRRcap_MSR 0x0fe +#define MTRRdefType_MSR 0x2ff + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +#define NUM_FIXED_RANGES 88 +#define MTRRfix64K_00000_MSR 0x250 +#define MTRRfix16K_80000_MSR 0x258 +#define MTRRfix16K_A0000_MSR 0x259 +#define MTRRfix4K_C0000_MSR 0x268 +#define MTRRfix4K_C8000_MSR 0x269 +#define MTRRfix4K_D0000_MSR 0x26a +#define MTRRfix4K_D8000_MSR 0x26b +#define MTRRfix4K_E0000_MSR 0x26c +#define MTRRfix4K_E8000_MSR 0x26d +#define MTRRfix4K_F0000_MSR 0x26e +#define MTRRfix4K_F8000_MSR 0x26f + +#if !defined (ASSEMBLY) + +void x86_setup_var_mtrrs(unsigned address_bits); +void x86_setup_mtrrs(unsigned address_bits); +int x86_mtrr_check(void); + +#endif + +#endif /* ARCH_X86_MTRR_H */
Modified: coreboot-v3/mainboard/Kconfig =================================================================== --- coreboot-v3/mainboard/Kconfig 2008-08-01 16:59:09 UTC (rev 701) +++ coreboot-v3/mainboard/Kconfig 2008-08-01 17:03:22 UTC (rev 702) @@ -42,6 +42,11 @@ help Select this option for various systems from the Artec Group.
+config VENDOR_GIGABYTE + bool "Gigabyte" + help + Select this option for various systems from Gigabyte + config VENDOR_EMULATION bool "Emulated systems" help @@ -58,6 +63,7 @@ source "mainboard/amd/Kconfig" source "mainboard/artecgroup/Kconfig" source "mainboard/emulation/Kconfig" +source "mainboard/gigabyte/Kconfig" source "mainboard/pcengines/Kconfig"
choice
Added: coreboot-v3/mainboard/gigabyte/Kconfig =================================================================== --- coreboot-v3/mainboard/gigabyte/Kconfig (rev 0) +++ coreboot-v3/mainboard/gigabyte/Kconfig 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_GIGABYTE + +config BOARD_GIGABYTE_M57SLI + bool "M57SLI" + select ARCH_X86 + select OPTION_TABLE + select CPU_AMD_K8 + help + Gigabyte M57SLI + +endchoice + +source "mainboard/gigabyte/m57sli/Kconfig"
Added: coreboot-v3/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Kconfig (rev 0) +++ coreboot-v3/mainboard/gigabyte/m57sli/Kconfig 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config MAINBOARD_NAME + string + default gigabyte/m57sli + depends BOARD_GIGABYTE_M57SLI + help + This is the default mainboard name.
Added: coreboot-v3/mainboard/gigabyte/m57sli/Makefile =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Makefile (rev 0) +++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o + +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c + +STAGE2_MAINBOARD_OBJ = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) +
Added: coreboot-v3/mainboard/gigabyte/m57sli/dts =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/dts (rev 0) +++ coreboot-v3/mainboard/gigabyte/m57sli/dts 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard_vendor = "Gigabyte"; + mainboard_name = "M57SLI"; + cpus { }; + apic@0 { + }; + domain@0 { + }; +};
Added: coreboot-v3/mainboard/gigabyte/m57sli/initram.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/initram.c (rev 0) +++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_k8.h> +#include <spd.h> + +/** + * main for initram for the Gigabyte m57sli. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from stage1\n"); + post_code(POST_START_OF_MAIN); + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +}
Added: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c (rev 0) +++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-08-01 17:03:22 UTC (rev 702) @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <arch/x86/msr.h> + +void hardware_stage1(void) +{ + post_code(POST_START_OF_MAIN); + +} + +void mainboard_pre_payload(void) +{ + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +}