Stefan Reinauer wrote:
RAM init working concurrently with multiple memory controllers - they're on PCI, right?
Yes.
But why would it not be completely sufficient to set up all ram controllers in the system from the BSP?
The big coreboot SMP win is with ECC scrubbing, right? Does that involve some PCI config space accesses to the memory controllers? Is it simpler to create locking for PCI accesses, or to split out the part of RAM init which sets up MCs into the BSP (as opposed to keeping the code for each MC running on that same core)?
I'm saying we're opening a can of worms here, and unless we really like to go fishing we should close it again and walk in the dry.
I'm thinking we're already hooked on that tasty fish? (By fish I mean SMP memory init.)
//Peter