Re: [coreboot] v3 cn700 patch dump

[Peter Stuge]

(This applies cleanly to v3 trunk.)

Corey Osgood wrote:
> Moves non-DRAM early init code out of initram and into stage1, where it should have been in the first place
> Fixes an issue with GP3 timer causing system reboot (possibly not present in current svn, but was present in my local copy)
> Fixes serial garbage from stage1 on jetway j7f2
> Fixes ROM mapping for flash > 512k on vt8237
> Checks that the CAR base + size allows for the selected ROM size
> Makes a couple minor whitespace changes
> Moves some function prototypes to the headers where they belong
> Nukes some phase2 hackery that belongs in phase4 (eventually)
> Comments out early_mtrr_init() for via/epia-cn, this breaks booting on jetway j7f2
> Moves troublesome SATA init code into stage1 - change of device class hangs coreboot
> Gets to vt8237 IDE phase6 init and dies on jetway/j7f2:
>  Phase 6: Initializing devices...                                                
>  Phase 6: Root Device init.                                                      
>  Phase 6: PCI: 00:10.1 init.                                                     
>  Primary IDE interface enabled                                                   
>  Secondary IDE interface enabled
>
>  <hang>
>
> Signed-off-by: Corey Osgood

Acked-by: Peter Stuge