Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

[Scott Duplichan]

Patrick Georgi wrote:

]Am Freitag, 23. September 2011 01:45:09 schrieb Oskar Enoksson:
]> As for the "dead" behaviour in recent versions I bisected my way down
]> to commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That
]> commit adds "TINY_BOOTBLOCK support"  to AMD-8111 southbridge. I
]> understand that this commit splits up things into a "romstage" and
]> "coreboot_ram". But what is going wrong, and what should I do? All
]> hints appreciated.
]Try a smaller image size (and write it into flash top-aligned). If 
]things work then, the bootblock doesn't correctly set up ROM mapping 
]correctly.

Hello Patrick,

That is a good point about rom mapping. According to the 8111 document,
only the top 64KB is decoded by default. Simnow confirms this, and
won't boot the DL145 G1coreboot image. Dumping the start of the 512KB
image shows it is not decoded:

-d fff80000
FFF80000-FF FF FF FF FF FF FF FF   FF FF FF FF FF FF FF FF

If I manually issue these PCI config writes while execution is still
in the top 64KB, the entire 512KB is decoded and simnow will boot
the coreboot image:

// write to AMD 8131 Link Command Register BUID field (bits 16-20)
// with value 2 so that the 8111 can be accessed:
-epcid 0 0 0 c0 00420008 // bus 0, dev 0, fun 0, reg 0xc0

// write to AMD 8111 Rom Decode Control Register and set bit 7
// to enable LPC memory decoding of the top 4MB of 4GB space:
-epcib 0 1 0 43 80 // bus 0, dev 1, fun 0, reg 0x43

-d fff80000
FFF80000-4C 41 52 43 48 49 56 45   00 00 06 F0 00 00 01 AA
LARCHIVE........

A couple of PCI config writes similar to these should get it going.

Thanks,
Scott