Author: mjones Date: 2008-10-28 00:16:17 +0100 (Tue, 28 Oct 2008) New Revision: 955
Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c coreboot-v3/southbridge/amd/amd8111/acpi.c coreboot-v3/southbridge/amd/amd8111/ide.c coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/amd8111/nic.c coreboot-v3/southbridge/amd/amd8111/pci.c coreboot-v3/southbridge/amd/amd8111/smbus.c coreboot-v3/southbridge/amd/amd8111/usb.c coreboot-v3/southbridge/amd/amd8111/usb2.c coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/rs690/gfx.c coreboot-v3/southbridge/amd/rs690/ht.c coreboot-v3/southbridge/amd/rs690/pcie.c coreboot-v3/southbridge/amd/sb600/ac97.c coreboot-v3/southbridge/amd/sb600/hda.c coreboot-v3/southbridge/amd/sb600/ide.c coreboot-v3/southbridge/amd/sb600/lpc.c coreboot-v3/southbridge/amd/sb600/pci.c coreboot-v3/southbridge/amd/sb600/sata.c coreboot-v3/southbridge/amd/sb600/sm.c coreboot-v3/southbridge/amd/sb600/usb.c Log: Whitespace cleanup on AMD southbridge device_operations structs. (trivial)
Signed-off-by: Marc Jones marc.jones@amd.com Acked-by: Marc Jones marc.jones@amd.com
Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-10-27 23:16:17 UTC (rev 955) @@ -41,10 +41,10 @@ struct device_operations ac97audio = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x746D}}}, + .device = 0x746D}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -55,10 +55,10 @@ struct device_operations ac97modem = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x746E}}}, + .device = 0x746E}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-10-27 23:16:17 UTC (rev 955) @@ -228,14 +228,14 @@ struct device_operations acpi = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ACPI}}}, + .device = PCI_DEVICE_ID_AMD_8111_ACPI}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = acpi_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = acpi_enable_resources, .phase6_init = acpi_init, .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_smbus_bus = &lops_smbus_bus, };
Modified: coreboot-v3/southbridge/amd/amd8111/ide.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-10-27 23:16:17 UTC (rev 955) @@ -75,13 +75,13 @@ struct device_operations amd8111_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_IDE}}}, + .device = PCI_DEVICE_ID_AMD_8111_IDE}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };
Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-10-27 23:16:17 UTC (rev 955) @@ -210,10 +210,10 @@ struct device_operations amd8111_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ISA}}}, + .device = PCI_DEVICE_ID_AMD_8111_ISA}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = amd8111_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = amd8111_lpc_enable_resources,
Modified: coreboot-v3/southbridge/amd/amd8111/nic.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-10-27 23:16:17 UTC (rev 955) @@ -96,10 +96,10 @@ struct device_operations amd8111_nic = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_NIC}}}, + .device = PCI_DEVICE_ID_AMD_8111_NIC}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/amd8111/pci.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/pci.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/pci.c 2008-10-27 23:16:17 UTC (rev 955) @@ -72,10 +72,10 @@ struct device_operations amd8111_pci = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, + .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources,
Modified: coreboot-v3/southbridge/amd/amd8111/smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-10-27 23:16:17 UTC (rev 955) @@ -50,14 +50,14 @@ struct device_operations amd8111_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_SMB}}}, + .device = PCI_DEVICE_ID_AMD_8111_SMB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
Modified: coreboot-v3/southbridge/amd/amd8111/usb.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-27 23:16:17 UTC (rev 955) @@ -47,13 +47,13 @@ struct device_operations amd8111_usb = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB}}}, + .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };
Modified: coreboot-v3/southbridge/amd/amd8111/usb2.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-10-27 23:16:17 UTC (rev 955) @@ -46,10 +46,10 @@ struct device_operations amd8111_usb2 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB}}}, + .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_usb2_enable, + .phase3_chip_setup_dev = amd8111_usb2_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c =================================================================== --- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-10-27 23:16:17 UTC (rev 955) @@ -348,16 +348,16 @@ struct device_operations amd8132_pcix = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8132_PCIX}}}, + .device = PCI_DEVICE_ID_AMD_8132_PCIX}}}, .constructor = default_device_constructor, - .reset_bus = pci_bus_reset, + .reset_bus = pci_bus_reset, .phase3_scan = amd8132_scan_bridge, #if BRIDGE_40_BIT_SUPPORT - .phase4_read_resources = bridge_read_resources, - .phase4_set_resources = bridge_set_resources, + .phase4_read_resources = bridge_read_resources, + .phase4_set_resources = bridge_set_resources, #else - .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, #endif .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = amd8132_pcix_init, @@ -422,10 +422,10 @@ struct device_operations amd8132_apic = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}}, + .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = ioapic_enable, + .phase4_enable_disable = ioapic_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase6_init = amd8132_ioapic_init,
Modified: coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c =================================================================== --- coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-10-27 23:16:17 UTC (rev 955) @@ -43,11 +43,11 @@ struct device_operations amd8151_agp3bridge = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8151_AGP}}}, + .device = PCI_DEVICE_ID_AMD_8151_AGP}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge - .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = agp3bridge_init, }; @@ -78,11 +78,11 @@ struct device_operations amd8151_agp3dev = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}}, + .device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}}, .constructor = default_device_constructor, - .phase4_enable_disable = agp3dev_enable, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_enable_disable = agp3dev_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-10-27 23:16:17 UTC (rev 955) @@ -712,19 +712,19 @@ struct device_operations cs5536_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase5_enable_resources = cs5536_pci_dev_enable_resources, - .phase6_init = southbridge_init, + .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = cs5536_pci_dev_enable_resources, + .phase6_init = southbridge_init, };
struct device_operations cs5536_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, + .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, .constructor = default_device_constructor, #warning FIXME: what has to go in phase3_scan? .phase3_scan = 0,
Modified: coreboot-v3/southbridge/amd/rs690/gfx.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-27 23:16:17 UTC (rev 955) @@ -563,10 +563,10 @@ struct device_operations rs690_gfx = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}}, + .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = rs690_enable, - .phase3_enable = rs690_internal_gfx_enable, + .phase3_chip_setup_dev = rs690_enable, + .phase3_enable = rs690_internal_gfx_enable, .phase3_scan = 0, .phase4_read_resources = rs690_gfx_read_resources, .phase4_set_resources = rs690_gfx_set_resources,
Modified: coreboot-v3/southbridge/amd/rs690/ht.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-27 23:16:17 UTC (rev 955) @@ -83,10 +83,10 @@ struct device_operations rs690_ht = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_HT}}}, + .device = PCI_DEVICE_ID_ATI_RS690_HT}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-27 23:16:17 UTC (rev 955) @@ -397,10 +397,10 @@ struct device_operations rs690_pcie = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase3_chip_setup_dev = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, @@ -412,7 +412,7 @@ struct device_operations rs690_pcie2 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -425,7 +425,7 @@ struct device_operations rs690_pcie3 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -438,7 +438,7 @@ struct device_operations rs690_pcie4 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -451,7 +451,7 @@ struct device_operations rs690_pcie5 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -464,7 +464,7 @@ struct device_operations rs690_pcie6 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -477,7 +477,7 @@ struct device_operations rs690_pcie7 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -490,7 +490,7 @@ struct device_operations rs690_pcie8 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources,
Modified: coreboot-v3/southbridge/amd/sb600/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-27 23:16:17 UTC (rev 955) @@ -35,10 +35,10 @@ struct device_operations ac97audio = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, + .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -49,10 +49,10 @@ struct device_operations ac97modem = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, + .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/hda.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-27 23:16:17 UTC (rev 955) @@ -277,12 +277,12 @@ struct device_operations sb600_hda = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, + .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = hda_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };
Modified: coreboot-v3/southbridge/amd/sb600/ide.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-27 23:16:17 UTC (rev 955) @@ -68,12 +68,12 @@ struct device_operations sb600_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, + .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };
Modified: coreboot-v3/southbridge/amd/sb600/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-27 23:16:17 UTC (rev 955) @@ -210,13 +210,13 @@ struct device_operations sb600_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, + .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = sb600_enable, + .phase3_scan = scan_static_bus, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };
Modified: coreboot-v3/southbridge/amd/sb600/pci.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-27 23:16:17 UTC (rev 955) @@ -127,13 +127,13 @@ struct device_operations sb600_pci = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_PCI}}}, + .device = PCI_DEVICE_ID_ATI_SB600_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, - .reset_bus = pci_bus_reset, + .reset_bus = pci_bus_reset, };
Modified: coreboot-v3/southbridge/amd/sb600/sata.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-27 23:16:17 UTC (rev 955) @@ -190,12 +190,12 @@ struct device_operations sb600_sata = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, + .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };
Modified: coreboot-v3/southbridge/amd/sb600/sm.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-27 23:16:17 UTC (rev 955) @@ -392,14 +392,14 @@ struct device_operations sb600_sm = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, + .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_sm_read_resources, .phase4_set_resources = sb600_sm_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sm_init, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
Modified: coreboot-v3/southbridge/amd/sb600/usb.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-27 23:16:17 UTC (rev 955) @@ -166,14 +166,14 @@ struct device_operations sb600_usb = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_0}}}, + .device = PCI_DEVICE_ID_ATI_SB600_USB_0}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };
#if 0 @@ -202,13 +202,13 @@ struct device_operations sb600_usb2 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, + .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };