Author: uwe Date: Fri Dec 17 23:34:58 2010 New Revision: 6197 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6197
Log: inteltool: Model 0xf2x, ICH5, i865 support.
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM registers on ICH5. Add ICH5 and i865 to the supported chips list. Enable the dumping of BAR6 on i865.
Sample output:
Disabling memory access: $ sudo setpci -s 6.0 0x04.b=0x0
$ sudo ./inteltool -m | head -n 9 Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7 Intel Northbridge: 8086:2570 (i865) Intel Southbridge: 8086:24d0 (ICH5)
============= MCHBAR ============
Access to BAR6 is currently disabled, attempting to enable. Enabled successfully. BAR6 = 0xfecf0000 (MEM)
Signed-off-by: Idwer Vollering vidwer@gmail.com Acked-by: Joseph Smith joe@settoplinux.org Acked-by: Peter Stuge peter@stuge.se Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/util/inteltool/cpu.c trunk/util/inteltool/gpio.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c trunk/util/inteltool/powermgt.c trunk/util/inteltool/rootcmplx.c
Modified: trunk/util/inteltool/cpu.c ============================================================================== --- trunk/util/inteltool/cpu.c Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/cpu.c Fri Dec 17 23:34:58 2010 (r6197) @@ -398,13 +398,214 @@ /* * All MSRs per * - * Intel� 64 and IA-32 Architectures - * Software Developer.s Manual - * Volume 3B: - * System Programming Guide, Part 2 + * Intel 64 and IA-32 Architectures Software Developer's Manual + * Volume 3B: System Programming Guide, Part 2 * - * Table B-5 + * Table B-5, B-7 */ + static const msr_entry_t modelf2x_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + /* 0x6: Not available in model 2. */ + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, + { 0x002b, "MSR_EBC_SOFT_POWRON" }, + /* 0x2c: Not available in model 2. */ +// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + { 0x019c, "IA32_THERM_STATUS" }, + /* 0x19d: Not available in model 2. */ + { 0x01a0, "IA32_MISC_ENABLE" }, + /* 0x1a1: Not available in model 2. */ + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + { 0x0302, "MSR_BPU_COUNTER2" }, + { 0x0303, "MSR_BPU_COUNTER3" }, + { 0x0304, "MSR_MS_COUNTER0" }, + { 0x0305, "MSR_MS_COUNTER1" }, + { 0x0306, "MSR_MS_COUNTER2" }, + { 0x0307, "MSR_MS_COUNTER3" }, + { 0x0308, "MSR_FLAME_COUNTER0" }, + { 0x0309, "MSR_FLAME_COUNTER1" }, + { 0x030a, "MSR_FLAME_COUNTER2" }, + { 0x030b, "MSR_FLAME_COUNTER3" }, + { 0x030c, "MSR_IQ_COUNTER0" }, + { 0x030d, "MSR_IQ_COUNTER1" }, + { 0x030e, "MSR_IQ_COUNTER2" }, + { 0x030f, "MSR_IQ_COUNTER3" }, + { 0x0310, "MSR_IQ_COUNTER4" }, + { 0x0311, "MSR_IQ_COUNTER5" }, + { 0x0360, "MSR_BPU_CCCR0" }, + { 0x0361, "MSR_BPU_CCCR1" }, + { 0x0362, "MSR_BPU_CCCR2" }, + { 0x0363, "MSR_BPU_CCCR3" }, + { 0x0364, "MSR_MS_CCCR0" }, + { 0x0365, "MSR_MS_CCCR1" }, + { 0x0366, "MSR_MS_CCCR2" }, + { 0x0367, "MSR_MS_CCCR3" }, + { 0x0368, "MSR_FLAME_CCCR0" }, + { 0x0369, "MSR_FLAME_CCCR1" }, + { 0x036a, "MSR_FLAME_CCCR2" }, + { 0x036b, "MSR_FLAME_CCCR3" }, + { 0x036c, "MSR_IQ_CCCR0" }, + { 0x036d, "MSR_IQ_CCCR1" }, + { 0x036e, "MSR_IQ_CCCR2" }, + { 0x036f, "MSR_IQ_CCCR3" }, + { 0x0370, "MSR_IQ_CCCR4" }, + { 0x0371, "MSR_IQ_CCCR5" }, + { 0x03a0, "MSR_BSU_ESCR0" }, + { 0x03a1, "MSR_BSU_ESCR1" }, + { 0x03a2, "MSR_FSB_ESCR0" }, + { 0x03a3, "MSR_FSB_ESCR1" }, + { 0x03a4, "MSR_FIRM_ESCR0" }, + { 0x03a5, "MSR_FIRM_ESCR1" }, + { 0x03a6, "MSR_FLAME_ESCR0" }, + { 0x03a7, "MSR_FLAME_ESCR1" }, + { 0x03a8, "MSR_DAC_ESCR0" }, + { 0x03a9, "MSR_DAC_ESCR1" }, + { 0x03aa, "MSR_MOB_ESCR0" }, + { 0x03ab, "MSR_MOB_ESCR1" }, + { 0x03ac, "MSR_PMH_ESCR0" }, + { 0x03ad, "MSR_PMH_ESCR1" }, + { 0x03ae, "MSR_SAAT_ESCR0" }, + { 0x03af, "MSR_SAAT_ESCR1" }, + { 0x03b0, "MSR_U2L_ESCR0" }, + { 0x03b1, "MSR_U2L_ESCR1" }, + { 0x03b2, "MSR_BPU_ESCR0" }, + { 0x03b3, "MSR_BPU_ESCR1" }, + { 0x03b4, "MSR_IS_ESCR0" }, + { 0x03b5, "MSR_BPU_ESCR1" }, + { 0x03b6, "MSR_ITLB_ESCR0" }, + { 0x03b7, "MSR_ITLB_ESCR1" }, + { 0x03b8, "MSR_CRU_ESCR0" }, + { 0x03b9, "MSR_CRU_ESCR1" }, + { 0x03ba, "MSR_IQ_ESCR0" }, + { 0x03bb, "MSR_IQ_ESCR1" }, + { 0x03bc, "MSR_RAT_ESCR0" }, + { 0x03bd, "MSR_RAT_ESCR1" }, + { 0x03be, "MSR_SSU_ESCR0" }, + { 0x03c0, "MSR_MS_ESCR0" }, + { 0x03c1, "MSR_MS_ESCR1" }, + { 0x03c2, "MSR_TBPU_ESCR0" }, + { 0x03c3, "MSR_TBPU_ESCR1" }, + { 0x03c4, "MSR_TC_ESCR0" }, + { 0x03c5, "MSR_TC_ESCR1" }, + { 0x03c8, "MSR_IX_ESCR0" }, + { 0x03c9, "MSR_IX_ESCR1" }, + { 0x03ca, "MSR_ALF_ESCR0" }, + { 0x03cb, "MSR_ALF_ESCR1" }, + { 0x03cc, "MSR_CRU_ESCR2" }, + { 0x03cd, "MSR_CRU_ESCR3" }, + { 0x03e0, "MSR_CRU_ESCR4" }, + { 0x03e1, "MSR_CRU_ESCR5" }, + { 0x03f0, "MSR_TC_PRECISE_EVENT" }, + { 0x03f1, "MSR_PEBS_ENABLE" }, + { 0x03f2, "MSR_PEBS_MATRIX_VERT" }, + + /* + * All MCX_ADDR and MCX_MISC MSRs depend on a bit being + * set in MCX_STATUS. + */ + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x403, "IA32_MC0_MISC" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x406, "IA32_MC1_ADDR" }, + { 0x407, "IA32_MC1_MISC" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x40b, "IA32_MC2_MISC" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x40f, "IA32_MC3_MISC" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, + { 0x412, "IA32_MC4_ADDR" }, + { 0x413, "IA32_MC4_MISC" }, + }; + + static const msr_entry_t modelf2x_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + /* 0x3a: Not available in model 2. */ + { 0x008b, "IA32_BIOS_SIGN_ID" }, + /* 0x9b: Not available in model 2. */ + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x017b, "IA32_MCG_CTL" }, + { 0x0180, "MSR_MCG_RAX" }, + { 0x0181, "MSR_MCG_RBX" }, + { 0x0182, "MSR_MCG_RCX" }, + { 0x0183, "MSR_MCG_RDX" }, + { 0x0184, "MSR_MCG_RSI" }, + { 0x0185, "MSR_MCG_RDI" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x018a, "MSR_MCG_MISC" }, + /* 0x18b-0x18f: Reserved */ + { 0x0190, "MSR_MCG_R8" }, + { 0x0191, "MSR_MCG_R9" }, + { 0x0192, "MSR_MCG_R10" }, + { 0x0193, "MSR_MCG_R11" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0195, "MSR_MCG_R13" }, + { 0x0196, "MSR_MCG_R14" }, + { 0x0197, "MSR_MCG_R15" }, + /* 0x198: Not available in model 2. */ + /* 0x199: Not available in model 2. */ + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x01d7, "MSR_LER_FROM_LIP" }, + { 0x01d8, "MSR_LER_TO_LIP" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01da, "MSR_LASTBRANCH_TOS" }, + { 0x01db, "MSR_LASTBRANCH_0" }, + { 0x01dd, "MSR_LASTBRANCH_2" }, + { 0x01de, "MSR_LASTBRANCH_3" }, + { 0x0277, "IA32_PAT" }, + /* 0x480-0x48b : Not available in model 2. */ + { 0x0600, "IA32_DS_AREA" }, + /* 0x0680 - 0x06cf Branch Records Skipped */ + }; + static const msr_entry_t modelf4x_global_msrs[] = { { 0x0000, "IA32_P5_MC_ADDR" }, { 0x0001, "IA32_P5_MC_TYPE" }, @@ -529,8 +730,6 @@
};
- - typedef struct { unsigned int model; const msr_entry_t *global_msrs; @@ -544,6 +743,7 @@ { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, + { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, };
@@ -619,5 +819,3 @@ #endif return 0; } - -
Modified: trunk/util/inteltool/gpio.c ============================================================================== --- trunk/util/inteltool/gpio.c Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/gpio.c Fri Dec 17 23:34:58 2010 (r6197) @@ -77,6 +77,22 @@ { 0x3C, 4, "RESERVED" } };
+static const io_register_t ich5_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "GPO_TTL"}, + { 0x18, 4, "GPO_BLINK"}, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, +}; + static const io_register_t ich6_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x08, 4, "RESERVED" }, @@ -231,6 +247,11 @@ gpio_registers = ich6_gpio_registers; size = ARRAY_SIZE(ich6_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_ICH5: + gpiobase = pci_read_word(sb, 0x58) & 0xfffc; + gpio_registers = ich5_gpio_registers; + size = ARRAY_SIZE(ich5_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: gpiobase = pci_read_word(sb, 0x58) & 0xfffc; @@ -286,4 +307,3 @@
return 0; } -
Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/inteltool.c Fri Dec 17 23:34:58 2010 (r6197) @@ -41,6 +41,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, @@ -54,7 +55,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, @@ -72,6 +73,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, @@ -327,7 +329,7 @@ }
if (dump_mchbar) { - print_mchbar(nb); + print_mchbar(nb, pacc); printf("\n\n"); }
Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/inteltool.h Fri Dec 17 23:34:58 2010 (r6197) @@ -24,7 +24,7 @@ #include <sys/io.h> #endif #if (defined(__MACH__) && defined(__APPLE__)) -/* DirectIO is available here: http://www.coresystems.de/en/directio */ +/* DirectHW is available here: http://www.coresystems.de/en/directhw */ #define __DARWIN__ #include <DirectIO/darwinio.h> #endif @@ -44,6 +44,7 @@ #define PCI_DEVICE_ID_INTEL_ICH2 0x2440 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 #define PCI_DEVICE_ID_INTEL_ICH6 0x2640 #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 @@ -66,6 +67,7 @@ #define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 #define PCI_DEVICE_ID_INTEL_82830M 0x3575 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82865 0x2570 #define PCI_DEVICE_ID_INTEL_82915 0x2580 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 @@ -114,7 +116,7 @@
unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); -int print_mchbar(struct pci_dev *nb); +int print_mchbar(struct pci_dev *nb, struct pci_access *pacc); int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb);
Modified: trunk/util/inteltool/memory.c ============================================================================== --- trunk/util/inteltool/memory.c Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/memory.c Fri Dec 17 23:34:58 2010 (r6197) @@ -25,15 +25,42 @@ /* * (G)MCH MMIO Config Space */ -int print_mchbar(struct pci_dev *nb) +int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) { int i, size = (16 * 1024); volatile uint8_t *mchbar; - uint64_t mchbar_phys; + uint64_t mchbar_phys; + struct pci_dev *nb_device6; /* "overflow device" on i865 */ + uint16_t pcicmd6;
printf("\n============= MCHBAR ============\n\n");
switch (nb->device_id) { + case PCI_DEVICE_ID_INTEL_82865: + /* + * On i865, the memory access enable/disable bit (MCHBAREN on + * i945/i965) is not in the MCHBAR (i945/i965) register but in + * the PCICMD6 register. BAR6 and PCICMD6 reside on device 6. + * + * The actual base address is in BAR6 on i865 where on + * i945/i965 the base address is in MCHBAR. + */ + nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */ + mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */ + pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */ + + /* Try to enable Memory Access Enable (MAE). */ + if (!(pcicmd6 & (1 << 1))) { + printf("Access to BAR6 is currently disabled, " + "attempting to enable.\n"); + pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1)); + if (pci_read_long(nb_device6, 0x04) & (1 << 1)) + printf("Enabled successfully.\n"); + else + printf("Enable FAILED!\n"); + } + mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */ + break; case PCI_DEVICE_ID_INTEL_82915: case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945GSE: @@ -54,8 +81,8 @@ mchbar_phys = pci_read_long(nb, 0x48);
/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. - * If it isn't, try to set it. This may fail, because there is - * some bit that locks that bit, and isn't in the public + * If it isn't, try to set it. This may fail, because there is + * some bit that locks that bit, and isn't in the public * datasheets. */
@@ -79,7 +106,7 @@ case PCI_DEVICE_ID_INTEL_82810E_MC: case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82830M: - printf("This northbrigde does not have MCHBAR.\n"); + printf("This northbridge does not have MCHBAR.\n"); return 1; case PCI_DEVICE_ID_INTEL_GS45: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; @@ -93,11 +120,17 @@ mchbar = map_physical(mchbar_phys, size);
if (mchbar == NULL) { - perror("Error mapping MCHBAR"); + if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) + perror("Error mapping BAR6"); + else + perror("Error mapping MCHBAR"); exit(1); }
- printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys); + if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) + printf("BAR6 = 0x%08llx (MEM)\n\n", mchbar_phys); + else + printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys);
for (i = 0; i < size; i += 4) { if (*(uint32_t *)(mchbar + i))
Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/pcie.c Fri Dec 17 23:34:58 2010 (r6197) @@ -55,7 +55,8 @@ case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810E_MC: case PCI_DEVICE_ID_INTEL_82830M: - printf("This northbrigde does not have EPBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865: + printf("This northbridge does not have EPBAR.\n"); return 1; default: printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); @@ -112,7 +113,8 @@ case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810E_MC: - printf("This northbrigde does not have DMIBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865: + printf("This northbridge does not have DMIBAR.\n"); return 1; case PCI_DEVICE_ID_INTEL_X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; @@ -174,7 +176,8 @@ case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810E_MC: - printf("Error: This northbrigde does not have PCIEXBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865: + printf("Error: This northbridge does not have PCIEXBAR.\n"); return 1; default: printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); @@ -245,5 +248,3 @@
return 0; } - -
Modified: trunk/util/inteltool/powermgt.c ============================================================================== --- trunk/util/inteltool/powermgt.c Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/powermgt.c Fri Dec 17 23:34:58 2010 (r6197) @@ -297,6 +297,32 @@ { 0x54, 4, "C3_RES (Mobile Only)" }, };
+static const io_register_t ich5_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, + { 0x14, 3, "RESERVED" }, + { 0x17, 9, "RESERVED" }, + { 0x20, 1, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2c, 4, "GPE0_EN" }, + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 1, "MON_SMI" }, + { 0x42, 2, "RESERVED" }, + { 0x44, 1, "DEVACT_STS" }, + { 0x48, 1, "DEVTRAP_EN" }, + { 0x50, 1, "RESERVED" }, + { 0x51, 15, "RESERVED" }, + { 0x60, 16, "RESERVED" }, +}; + static const io_register_t ich4_pm_registers[] = { { 0x00, 2, "PM1_STS" }, { 0x02, 2, "PM1_EN" }, @@ -569,6 +595,11 @@ pm_registers = ich6_pm_registers; size = ARRAY_SIZE(ich6_pm_registers); break; + case PCI_DEVICE_ID_INTEL_ICH5: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich5_pm_registers; + size = ARRAY_SIZE(ich5_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH4: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich4_pm_registers; @@ -629,4 +660,3 @@
return 0; } -
Modified: trunk/util/inteltool/rootcmplx.c ============================================================================== --- trunk/util/inteltool/rootcmplx.c Fri Dec 17 19:04:26 2010 (r6196) +++ trunk/util/inteltool/rootcmplx.c Fri Dec 17 23:34:58 2010 (r6197) @@ -53,6 +53,7 @@ case PCI_DEVICE_ID_INTEL_ICH2: case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: + case PCI_DEVICE_ID_INTEL_ICH5: printf("This southbridge does not have RCBA.\n"); return 1; default: @@ -77,4 +78,3 @@ unmap_physical((void *)rcba, size); return 0; } -