[coreboot] r3198 - in trunk/coreboot-v2/src: mainboard/intel/mtarvon southbridge/intel/i3100

Author: uwe
Date: 2008-03-30 13:31:15 +0200 (Sun, 30 Mar 2008)
New Revision: 3198

Modified:
   trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
Log:
Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots
the system automatically unless software resets the timer
periodically. The extra reboot extends boot time by several seconds.

The attached patch adds a function to the Intel 3100 southbridge code
that halts the TCO timer, thus preventing this extra reboot, and calls
the function early in the boot process on the Mt. Arvon board.

It also fixes a bug in the LPC device initialization -- the ACPI BAR
enable flag is bit 7, not bit 4.

Signed-off-by: Ed Swierk 
Acked-by: Uwe Hermann

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c	2008-03-29 17:24:58 UTC (rev 3197)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c	2008-03-30 11:31:15 UTC (rev 3198)
@@ -90,6 +90,9 @@
    uart_init();
    console_init();

+	/* Prevent the TCO timer from rebooting us */
+	i3100_halt_tco_timer();
+
    /* Halt if there was a built in self test failure */
    report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-03-29 17:24:58 UTC (rev 3197)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-03-30 11:31:15 UTC (rev 3198)
@@ -30,3 +30,23 @@
    /* Enable decoding of I/O locations for SuperIO devices */
    pci_write_config16(dev, 0x82, 0x340f);
 }
+
+static void i3100_halt_tco_timer(void)
+{
+	device_t dev;
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				       PCI_DEVICE_ID_INTEL_3100_LPC), 0);
+	if (dev == PCI_DEV_INVALID) {
+		die("LPC bridge not found\r\n");
+	}
+
+	/* Temporarily enable the ACPI I/O range at 0x4000 */
+	pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
+	pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
+
+	/* Halt the TCO timer, preventing SMI and automatic reboot */
+	outw(inw(0x4068) | (1 << 11), 0x4068);
+
+	/* Disable the ACPI I/O range */
+	pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7));
+}

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c	2008-03-29 17:24:58 UTC (rev 3197)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c	2008-03-30 11:31:15 UTC (rev 3198)
@@ -276,7 +276,7 @@

/* Enable the ACPI bar */
    acpi_cntl = pci_read_config8(dev, 0x44);
-	acpi_cntl |= (1 << 4);
+	acpi_cntl |= (1 << 7);
    pci_write_config8(dev, 0x44, acpi_cntl);

/* Enable the GPIO bar */