Re: [LinuxBIOS] PATCH: add the pcengines ALIX1

[Uwe Hermann]

On Sat, Sep 08, 2007 at 09:28:34AM -0700, ron minnich wrote:
> Hi, here is try 2. This one builds :-)

Yep, confirmed :)
> Index: src/mainboard/pcengines/alix1c/Config.lb
>
> --- src/mainboard/pcengines/alix1c/Config.lb	(revision 0)
> +++ src/mainboard/pcengines/alix1c/Config.lb	(revision 0)

Add a license header, please.
> @@ -0,0 +1,206 @@
> +##
> +## Compute the location and size of where this firmware image
> +## (linuxBIOS plus bootloader) will live in the boot rom chip.
> +##
> +if USE_FALLBACK_IMAGE
> default ROM_SECTION_SIZE   = FALLBACK_SIZE
> default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
>
> +else
> default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
> default ROM_SECTION_OFFSET = 0
>
> +end
>
> +##
> +## Compute the start location and size size of
> +## The linuxBIOS bootloader.
> +##
> +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
> +default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
>
> +##
> +## Compute where this copy of linuxBIOS will start in the boot rom
> +##
> +default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
>
> +##
> +## Compute a range of ROM that can cached to speed up linuxBIOS,
> +## execution speed.
> +##
> +## XIP_ROM_SIZE must be a power of 2.
> +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
> +##
> +default XIP_ROM_SIZE=65536
> +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
>
> +##
> +## Set all of the defaults for an x86 architecture
> +##
>
> +arch i386 end
>
> +##
> +## Build the objects we have code for in this directory.
> +##
>
> +driver mainboard.o
>
> +if HAVE_PIRQ_TABLE
> object irq_tables.o
>
> +end
>
> +if USE_DCACHE_RAM
> #compile cache_as_ram.c to auto.inc
> makerule ./cache_as_ram_auto.inc
> 	depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
> 	action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
> 	action "perl -e 's/.rodata/.rom.data/g' -pi $@"
> 	action "perl -e 's/.text/.section .rom.text/g' -pi $@"
> end
>
> +end
>
> +##
> +## Build our 16 bit and 32 bit linuxBIOS entry code
> +##
> +mainboardinit cpu/x86/16bit/entry16.inc
> +mainboardinit cpu/x86/32bit/entry32.inc
> +ldscript /cpu/x86/16bit/entry16.lds
> +ldscript /cpu/x86/32bit/entry32.lds
>
> +##
> +## Build our reset vector (This is where linuxBIOS is entered)
> +##
> +if USE_FALLBACK_IMAGE
> mainboardinit cpu/x86/16bit/reset16.inc
> ldscript /cpu/x86/16bit/reset16.lds
>
> +else
> mainboardinit cpu/x86/32bit/reset32.inc
> ldscript /cpu/x86/32bit/reset32.lds
>
> +end
>
> +### Should this be in the northbridge code?
> +mainboardinit arch/i386/lib/cpu_reset.inc
>
> +##
> +## Include an id string (For safe flashing)
> +##
> +mainboardinit arch/i386/lib/id.inc
> +ldscript /arch/i386/lib/id.lds
>
> +###
> +### This is the early phase of linuxBIOS startup 
> +### Things are delicate and we test to see if we should
> +### failover to another image.
> +###
> +if USE_FALLBACK_IMAGE
> ldscript /arch/i386/lib/failover.lds
>
> +#	mainboardinit ./failover.inc
> +end
>
> +###
> +### O.k. We aren't just an intermediary anymore!
> +###
>
> +##
> +## Setup RAM
> +##
> +mainboardinit cpu/x86/fpu/enable_fpu.inc
>
> +if USE_DCACHE_RAM
> mainboardinit cpu/amd/model_lx/cache_as_ram.inc
> mainboardinit ./cache_as_ram_auto.inc
>
> +end
>
> +##
> +## Include the secondary Configuration files 
> +##
> +dir /pc80
> +config chip.h
>
> +chip northbridge/amd/lx
> device pci_domain 0 on
> 	device pci 1.0 on end
> device pci 1.1 on end
>  		chip southbridge/amd/cs5536
> 	# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
> 	# SIRQ Mode = Active(Quiet) mode. Save power....
> 	# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
> 	# How to get these? Boot linux and do this:
> 	# rdmsr 0x51400025
> 	register "lpc_serirq_enable" = "0x000010da"
> 	# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
> 	register "lpc_serirq_polarity" = "0x0000EF25"
> 	# mode is high 10 bits (determined from code)
> 	register "lpc_serirq_mode" = "1"
> 	# Don't yet know how to find this.
> 	register "enable_gpio_int_route" = "0x0D0C0700"
> 	register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
> 	register "enable_USBP4_device" = "0"	#0: host, 1:device
> 	register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
> 	register "com1_enable" = "0"
> 	register "com1_address" = "0x3F8"
> 	register "com1_irq" = "4"
> 	register "com2_enable" = "0"
> 	register "com2_address" = "0x2F8"
> 	register "com2_irq" = "3"
> 	register "unwanted_vpci[0]" = "0"	# End of list has a zero
>    			device pci f.0 on	# ISA Bridge
> 		chip superio/winbond/w83627hf
> 			device pnp 2e.0 off #  Floppy
> 				io 0x60 = 0x3f0
> 				irq 0x70 = 6
> 				drq 0x74 = 2
> 			end
> 			device pnp 2e.1 on #  Parallel Port
> 				io 0x60 = 0x378
> 				irq 0x70 = 7
> 			end
> 			device pnp 2e.2 on #  Com1
> 				io 0x60 = 0x3f8
> 				irq 0x70 = 4
> 			end
> 			device pnp 2e.3 on #  Com2
> 				io 0x60 = 0x2f8
> 				irq 0x70 = 3
> 			end
> 			device pnp 2e.5 on #  Keyboard
> 				io 0x60 = 0x60
> 				io 0x62 = 0x64
> 				irq 0x70 = 1
> 				irq 0x72 = 12
> 			end
> 			device pnp 2e.6 off #  CIR
> 				io 0x60 = 0x100
> 			end
> 			device pnp 2e.7 off #  GAME_MIDI_GIPO1
> 				io 0x60 = 0x220
> 				io 0x62 = 0x300
> 				irq 0x70 = 9
> 			end						
> 			device pnp 2e.8 on end #  GPIO2
> 			device pnp 2e.9 on end #  GPIO3
> 			device pnp 2e.a on end #  ACPI
> 			device pnp 2e.b on #  HW Monitor
> 				io 0x60 = 0x290
> 				irq 0x70 = 5
> 			end
> 		end
> 	end
> 	device pci f.1 on end	# Flash controller
> 	device pci f.2 on end	# IDE controller
>    			device pci f.3 on end 	# Audio
>    			device pci f.4 on end	# OHCI
> 	device pci f.5 on end	# EHCI
>  		end
> end
> # APIC cluster is late CPU init.
> device apic_cluster 0 on
> chip cpu/amd/model_lx
> 	device apic 0 on end
> end
> end
>
> +end
> Index: src/mainboard/pcengines/alix1c/reset.c
>
> --- src/mainboard/pcengines/alix1c/reset.c	(revision 0)
> +++ src/mainboard/pcengines/alix1c/reset.c	(revision 0)
> @@ -0,0 +1,43 @@
> +#if 0

As it's commented out (and likely copied from some other target), please
drop the file completely for now. We can add a working version (or
preferrably use a global/common file if possible) if and when we need it.
I don't like adding dummy files which aren't really necessary.

Is this file even used ATM? I see a
  default HAVE_HARD_RESET=0
in Options.lb.
> +//#include "arch/romcc_io.h"
> +#include <arch/io.h>
>
> +typedef unsigned device_t;
>
> +#define PCI_DEV(BUS, DEV, FN) ( \
> (((BUS) & 0xFF) << 16) | \
> (((DEV) & 0x1f) << 11) | \
> (((FN)  & 0x7) << 8))
>
> +static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
> +{
>    unsigned addr;
>    addr = dev | where;
>    outl(0x80000000 | (addr & ~3), 0xCF8);
>    outb(value, 0xCFC + (addr & 3));
>
> +}
>
> +static void pci_write_config32(device_t dev, unsigned where, unsigned value)
> +{
> unsigned addr;
>    addr = dev | where;
>    outl(0x80000000 | (addr & ~3), 0xCF8);
>    outl(value, 0xCFC);
>
> +}
>
> +static unsigned pci_read_config32(device_t dev, unsigned where)
> +{
> unsigned addr;
>    addr = dev | where;
>    outl(0x80000000 | (addr & ~3), 0xCF8);
>    return inl(0xCFC);
>
> +}
>
> +#include "../../../northbridge/amd/amdk8/reset_test.c"
>
> +void hard_reset(void)
> +{
> set_bios_reset();
> pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
>
> +}
> +#endif
> Index: src/mainboard/pcengines/alix1c/irq_tables.c
>
> --- src/mainboard/pcengines/alix1c/irq_tables.c	(revision 0)
> +++ src/mainboard/pcengines/alix1c/irq_tables.c	(revision 0)
> @@ -0,0 +1,107 @@
> +/*
> This file is part of the LinuxBIOS project.
> Copyright (C) 2007 Advanced Micro Devices, Inc.
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License version 2 as
> published by the Free Software Foundation.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +#include <arch/pirq_routing.h>
> +#include <console/console.h>
> +#include <arch/io.h>
> +#include <arch/pirq_routing.h>
> +#include "../../../southbridge/amd/cs5536/cs5536.h"
>
> +/* Platform IRQs */
> +#define PIRQA 11
> +#define PIRQB 5
> +#define PIRQC 10
> +#define PIRQD 10
>
> +/* Map */
> +#define M_PIRQA (1 << PIRQA)  /* Bitmap of supported IRQs */
> +#define M_PIRQB (1 << PIRQB)  /* Bitmap of supported IRQs */
> +#define M_PIRQC (1 << PIRQC)  /* Bitmap of supported IRQs */
> +#define M_PIRQD (1 << PIRQD)  /* Bitmap of supported IRQs */
>
> +/* Link */
> +#define L_PIRQA  1 /* Means Slot INTx# Connects To Chipset INTA# */
> +#define L_PIRQB  2 /* Means Slot INTx# Connects To Chipset INTB# */
> +#define L_PIRQC  3 /* Means Slot INTx# Connects To Chipset INTC# */
> +#define L_PIRQD  4 /* Means Slot INTx# Connects To Chipset INTD# */
>
> +const struct irq_routing_table intel_irq_routing_table = {
> PIRQ_SIGNATURE,  /* u32 signature */
> PIRQ_VERSION,    /* u16 version   */
> 32+16*9,	 /* There can be total 9 devices on the bus */

Is the 9 (and the rest of this file) correct and tested?

Below in Options.lb there's a
  default IRQ_SLOT_COUNT=6
which contradicts the 9 here(?)
> 0x00,		 /* Where the interrupt router lies (bus) */
> (0x0f<<3)|0x0,   /* Where the interrupt router lies (dev) */
> 0,		 /* IRQs devoted exclusively to PCI usage */
> 0x100b,		 /* Vendor */
> 0x2b,		 /* Device */
> 0,		 /* Crap (miniport) */
> { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
> 0xe,		 /* u8 checksum. This has to be set to some
> 	    value that would give 0 after the sum of all
> 	    bytes for this structure (including checksum) */
> {
> /* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
> {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
> {0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
> {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
> {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
> {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
> {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
> {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
> {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
> {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
> }
>
> +};
>
> +unsigned long write_pirq_routing_table(unsigned long addr){
>   int i, j, k, num_entries;
>   unsigned int pirq[4];
>   uint16_t chipset_irq_map;
>   uint32_t pciAddr, pirtable_end;
>   struct irq_routing_table *pirq_tbl;
>   pirtable_end = copy_pirq_routing_table(addr);
>   /* Set up chipset IRQ steering */
>   pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
>   chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10);
>   printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
>   outl(pciAddr & ~3, 0xCF8);
>   outl(chipset_irq_map, 0xCFC);
>   pirq_tbl = (struct irq_routing_table *)(addr);
>   num_entries = (pirq_tbl->size - 32)/16;
>   /* Set PCI IRQs */
>   for (i=0; i < num_entries; i++){
>           printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
>           for (j = 0; j < 4; j++){
>           printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
>                   for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
>                   pirq[j] = k;
>                   printk_debug("PIRQ: %d\n", k);
>           }
>           pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq);        /* bus, device, slots IRQs for {A,B,C,D} */
>   }
>   /* put the PIR table in memory and checksum */
>   return pirtable_end;
>
> +}
> Index: src/mainboard/pcengines/alix1c/Options.lb
>
> --- src/mainboard/pcengines/alix1c/Options.lb	(revision 0)
> +++ src/mainboard/pcengines/alix1c/Options.lb	(revision 0)

Add a license header, please.
> @@ -0,0 +1,179 @@
> +uses HAVE_MP_TABLE
> +uses HAVE_PIRQ_TABLE
> +uses USE_FALLBACK_IMAGE
> +uses HAVE_FALLBACK_BOOT
> +uses HAVE_HARD_RESET
> +uses HAVE_OPTION_TABLE
> +uses USE_OPTION_TABLE
> +uses CONFIG_ROM_PAYLOAD
> +uses IRQ_SLOT_COUNT
> +uses MAINBOARD
> +uses MAINBOARD_VENDOR
> +uses MAINBOARD_PART_NUMBER
> +uses LINUXBIOS_EXTRA_VERSION
> +uses ARCH
> +uses FALLBACK_SIZE
> +uses STACK_SIZE
> +uses HEAP_SIZE
> +uses ROM_SIZE
> +uses ROM_SECTION_SIZE
> +uses ROM_IMAGE_SIZE
> +uses ROM_SECTION_SIZE
> +uses ROM_SECTION_OFFSET
> +uses CONFIG_ROM_PAYLOAD_START
> +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
> +uses CONFIG_COMPRESSED_PAYLOAD_LZMA
> +uses CONFIG_PRECOMPRESSED_PAYLOAD
> +uses PAYLOAD_SIZE
> +uses _ROMBASE
> +uses _RAMBASE
> +uses XIP_ROM_SIZE
> +uses XIP_ROM_BASE
> +uses HAVE_MP_TABLE
> +uses CROSS_COMPILE
> +uses CC
> +uses HOSTCC
> +uses OBJCOPY
> +uses DEFAULT_CONSOLE_LOGLEVEL
> +uses MAXIMUM_CONSOLE_LOGLEVEL
> +uses CONFIG_CONSOLE_SERIAL8250
> +uses TTYS0_BAUD
> +uses TTYS0_BASE
> +uses TTYS0_LCS
> +uses CONFIG_UDELAY_TSC
> +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
> +uses CONFIG_CONSOLE_VGA
> +uses CONFIG_PCI_ROM_RUN
> +uses CONFIG_VIDEO_MB
> +uses USE_DCACHE_RAM
> +uses DCACHE_RAM_BASE
> +uses DCACHE_RAM_SIZE
>
> +## ROM_SIZE is the size of boot ROM that this board will use.
> +default ROM_SIZE  = 512*1024
>
> +###
> +### Build options
> +###
> +default CONFIG_CONSOLE_VGA=0
> +default CONFIG_VIDEO_MB=8
> +default CONFIG_PCI_ROM_RUN=0
>
> +##
> +## Build code for the fallback boot
> +##
> +default HAVE_FALLBACK_BOOT=1
>
> +##
> +## no MP table
> +##
> +default HAVE_MP_TABLE=0
>
> +##
> +## Build code to reset the motherboard from linuxBIOS
> +##
> +default HAVE_HARD_RESET=0
>
> +## Delay timer options
> +##
> +default CONFIG_UDELAY_TSC=1
> +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
>
> +##
> +## Build code to export a programmable irq routing table
> +##
> +default HAVE_PIRQ_TABLE=1
> +default IRQ_SLOT_COUNT=6
> +#object irq_tables.o
>
> +##
> +## Build code to export a CMOS option table
> +##
> +default HAVE_OPTION_TABLE=0
>
> +###
> +### LinuxBIOS layout values
> +###
>
> +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
> +default ROM_IMAGE_SIZE = 65536
> +default FALLBACK_SIZE = 131072
>
> +##
> +## enable CACHE_AS_RAM specifics
> +##
> +default USE_DCACHE_RAM=1
> +default DCACHE_RAM_BASE=0xc8000
> +default DCACHE_RAM_SIZE=0x08000
>
> +##
> +## Use a small 8K stack
> +##
> +default STACK_SIZE=0x2000
>
> +##
> +## Use a small 16K heap
> +##
> +default HEAP_SIZE=0x4000
>
> +##
> +## Only use the option table in a normal image
> +##
> +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
> +default USE_OPTION_TABLE = 0
>
> +default _RAMBASE = 0x00004000
>
> +default CONFIG_ROM_PAYLOAD     = 1
>
> +##
> +## The default compiler
> +##
> +default CROSS_COMPILE=""
> +default CC="$(CROSS_COMPILE)gcc -m32"
> +default HOSTCC="gcc"
>
> +##
> +## The Serial Console
> +##
>
> +# To Enable the Serial Console
> +default CONFIG_CONSOLE_SERIAL8250=1
>
> +## Select the serial console baud rate
> +default TTYS0_BAUD=115200
> +#default TTYS0_BAUD=57600
> +#default TTYS0_BAUD=38400
> +#default TTYS0_BAUD=19200
> +#default TTYS0_BAUD=9600
> +#default TTYS0_BAUD=4800
> +#default TTYS0_BAUD=2400
> +#default TTYS0_BAUD=1200
>
> +# Select the serial console base port
> +default TTYS0_BASE=0x3f8
>
> +# Select the serial protocol
> +# This defaults to 8 data bits, 1 stop bit, and no parity
> +default TTYS0_LCS=0x3
>
> +##
> +### Select the linuxBIOS loglevel
> +##
> +## EMERG      1   system is unusable               
> +## ALERT      2   action must be taken immediately 
> +## CRIT       3   critical conditions              
> +## ERR        4   error conditions                 
> +## WARNING    5   warning conditions               
> +## NOTICE     6   normal but significant condition 
> +## INFO       7   informational                    
> +## DEBUG      8   debug-level messages             
> +## SPEW       9   Way too many details
>
> +## Request this level of debugging output
> +default  DEFAULT_CONSOLE_LOGLEVEL=8
> +## At a maximum only compile in this level of debugging
> +default  MAXIMUM_CONSOLE_LOGLEVEL=8
>
> +end
> Index: src/mainboard/pcengines/alix1c/debug.c
>
> --- src/mainboard/pcengines/alix1c/debug.c	(revision 0)
> +++ src/mainboard/pcengines/alix1c/debug.c	(revision 0)

NACK. Not yet another copy of this file, please. Move it into lib/ or
somewhere globally, and use that in all targets. We should stop
replicating there files again and again.
> @@ -0,0 +1,66 @@
>
> +static void print_debug_pci_dev(unsigned dev)
> +{
> print_debug("PCI: ");
> print_debug_hex8((dev >> 16) & 0xff);
> print_debug_char(':');
> print_debug_hex8((dev >> 11) & 0x1f);
> print_debug_char('.');
> print_debug_hex8((dev >> 8) & 7);
>
> +}
>
> +static void print_pci_devices(void)
> +{
> device_t dev;
> for(dev = PCI_DEV(0, 0, 0);
> dev <= PCI_DEV(0, 0x1f, 0x7); 
> dev += PCI_DEV(0,0,1)) {
> uint32_t id;
> id = pci_read_config32(dev, PCI_VENDOR_ID);
> if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
> 	(((id >> 16) & 0xffff) == 0xffff) ||
> 	(((id >> 16) & 0xffff) == 0x0000)) {
> 	continue;
> }
> print_debug_pci_dev(dev);
> print_debug("\r\n");
> }
>
> +}
>
> +static void dump_pci_device(unsigned dev)
> +{
> int i;
> print_debug_pci_dev(dev);
> print_debug("\r\n");
> for(i = 0; i <= 255; i++) {
> unsigned char val;
> if ((i & 0x0f) == 0) {
> 	print_debug_hex8(i);
> 	print_debug_char(':');
> }
> val = pci_read_config8(dev, i);
> print_debug_char(' ');
> print_debug_hex8(val);
> if ((i & 0x0f) == 0x0f) {
> 	print_debug("\r\n");
> }
> }
>
> +}
>
> +static void dump_pci_devices(void)
> +{
> device_t dev;
> for(dev = PCI_DEV(0, 0, 0);
> dev <= PCI_DEV(0, 0x1f, 0x7); 
> dev += PCI_DEV(0,0,1)) {
> uint32_t id;
> id = pci_read_config32(dev, PCI_VENDOR_ID);
> if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
> 	(((id >> 16) & 0xffff) == 0xffff) ||
> 	(((id >> 16) & 0xffff) == 0x0000)) {
> 	continue;
> }
> dump_pci_device(dev);
> }
>
> +}
> Index: src/mainboard/pcengines/alix1c/failover.c
> ===================================================================
> --- src/mainboard/pcengines/alix1c/failover.c	(revision 0)
> +++ src/mainboard/pcengines/alix1c/failover.c	(revision 0)

NACK, see above. This is common code just about every board duplicateѕ
again and again. I have a patch which adds a global failover.c into
lib/ (which my recent i810 board patch already uses, btw).

I'll post the patch ASAP.
> Index: src/mainboard/pcengines/alix1c/chip.h
>
> --- src/mainboard/pcengines/alix1c/chip.h	(revision 0)
> +++ src/mainboard/pcengines/alix1c/chip.h	(revision 0)

Trivial, but please add a license header.
> @@ -0,0 +1,5 @@
> +extern struct chip_operations mainboard_pcengines_alix1c_ops;
>
> +struct mainboard_pcengines_alix1c_config {
> int nothing;
>
> +};
> Index: src/mainboard/pcengines/alix1c/cmos.layout
> ===================================================================
> --- src/mainboard/pcengines/alix1c/cmos.layout	(revision 0)
> +++ src/mainboard/pcengines/alix1c/cmos.layout	(revision 0)

This should be dropped for now (needs a small fix in Config.lb to make
it still compile), as you use

default HAVE_OPTION_TABLE=0

above.
> @@ -0,0 +1,74 @@
> +entries
>
> +#start-bit length  config config-ID    name
> +#0            8       r       0        seconds
> +#8            8       r       0        alarm_seconds
> +#16           8       r       0        minutes
> +#24           8       r       0        alarm_minutes
> +#32           8       r       0        hours
> +#40           8       r       0        alarm_hours
> +#48           8       r       0        day_of_week
> +#56           8       r       0        day_of_month
> +#64           8       r       0        month
> +#72           8       r       0        year
> +#80           4       r       0        rate_select
> +#84           3       r       0        REF_Clock
> +#87           1       r       0        UIP
> +#88           1       r       0        auto_switch_DST
> +#89           1       r       0        24_hour_mode
> +#90           1       r       0        binary_values_enable
> +#91           1       r       0        square-wave_out_enable
> +#92           1       r       0        update_finished_enable
> +#93           1       r       0        alarm_interrupt_enable
> +#94           1       r       0        periodic_interrupt_enable
> +#95           1       r       0        disable_clock_updates
> +#96         288       r       0        temporary_filler
> +0          384       r       0        reserved_memory
> +384          1       e       4        boot_option
> +385          1       e       4        last_boot
> +386          1       e       1        ECC_memory
> +388          4       r       0        reboot_bits
> +392          3       e       5        baud_rate
> +400          1       e       1        power_on_after_fail
> +412          4       e       6        debug_level
> +416          4       e       7        boot_first
> +420          4       e       7        boot_second
> +424          4       e       7        boot_third
> +428          4       h       0        boot_index
> +432	     8       h       0        boot_countdown
> +1008         16      h       0        check_sum
>
> +enumerations
>
> +#ID value   text
> +1     0     Disable
> +1     1     Enable
> +2     0     Enable
> +2     1     Disable
> +4     0     Fallback
> +4     1     Normal
> +5     0     115200
> +5     1     57600
> +5     2     38400
> +5     3     19200
> +5     4     9600
> +5     5     4800
> +5     6     2400
> +5     7     1200
> +6     6     Notice
> +6     7     Info
> +6     8     Debug
> +6     9     Spew
> +7     0     Network
> +7     1     HDD
> +7     2     Floppy
> +7     8     Fallback_Network
> +7     9     Fallback_HDD
> +7     10    Fallback_Floppy
> +#7     3     ROM
>
> +checksums
>
> +checksum 392 1007 1008
> Index: src/mainboard/pcengines/alix1c/mainboard.c
>
> --- src/mainboard/pcengines/alix1c/mainboard.c	(revision 0)
> +++ src/mainboard/pcengines/alix1c/mainboard.c	(revision 0)

Add a license header, please.
> @@ -0,0 +1,154 @@
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include <arch/io.h>
> +#include <cpu/x86/msr.h>
> +#include <cpu/amd/lxdef.h>
> +#include "../../../southbridge/amd/cs5536/cs5536.h"
> +#include "chip.h"
>
> +/* Print the platform configuration */
> +void print_conf(void) {

Is this really needed here? Should it go in some common lib/ file?
Doesn't look board-specific to me.
> +#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
> int i;
> unsigned long iol;
> msr_t msr;
> int cpu_msr_defs[] =  { CPU_BC_L2_CONF, CPU_IM_CONFIG,
> 					CPU_DM_CONFIG0,  CPU_RCONF_DEFAULT,
> 					CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
> 					CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
> 					};
> int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,  MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
> 					 GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
> 					 GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
> 					 GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
> 					 GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
> 					 GLIU0_GLD_MSR_COH, GL_END
> 					};
> int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
> 					 MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
> 					 GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
> 					 GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
> 					 GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
> 					 GLIU1_GLD_MSR_COH, GL_END
> 					};
> int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
> 				CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
> 					};
> int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
> 				 MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
> 					};
> int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
> 			  GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
> 				 GL_END
> 					};
> int dma_msr[] =	 { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
> 					MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
> 					MDD_DMA_SHAD9, GL_END
> 					};
> printk_debug("---------- CPU ------------\n");
> for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
> msr = rdmsr(cpu_msr_defs[i]);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
> }
> printk_debug("---------- GLIU 0 ------------\n");
> for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
> msr = rdmsr(gliu0_msr_defs[i]);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
> }
> printk_debug("---------- GLIU 1 ------------\n");
> for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
> msr = rdmsr(gliu1_msr_defs[i]);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
> }
> printk_debug("---------- RCONF ------------\n");
> for(i = 0; rconf_msr[i] != GL_END; i++) {
> msr = rdmsr(rconf_msr[i]);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
> }
> printk_debug("---------- VARIA ------------\n");
> msr = rdmsr(0x51300010);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
> msr = rdmsr(0x51400015);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
> printk_debug("---------- DIVIL IRQ ------------\n");
> msr = rdmsr(MDD_IRQM_YLOW);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
> msr = rdmsr(MDD_IRQM_YHIGH);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
> msr = rdmsr(MDD_IRQM_ZLOW);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
> msr = rdmsr(MDD_IRQM_ZHIGH);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
> printk_debug("---------- PCI ------------\n");
> for(i = 0; pci_msr[i] != GL_END; i++) {
> msr = rdmsr(pci_msr[i]);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
> }
> printk_debug("---------- LPC/UART DMA ------------\n");
> for(i = 0; dma_msr[i] != GL_END; i++) {
> msr = rdmsr(dma_msr[i]);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
> }
> printk_debug("---------- CS5536 ------------\n");
> for(i = 0; cs5536_msr[i] != GL_END; i++) {
> msr = rdmsr(cs5536_msr[i]);
> printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
> }
> iol = inl(GPIOL_INPUT_ENABLE);
> printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol);
> iol = inl(GPIOL_EVENTS_ENABLE);
> printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol);
> iol = inl(GPIOL_INPUT_INVERT_ENABLE);
> printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol);
> iol = inl(GPIO_MAPPER_X);
> printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
>
> +#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
> +}
>
> +static void init(struct device *dev) {
> printk_debug("ALIX1C ENTER %s\n", __FUNCTION__);
> printk_debug("ALIX1C EXIT %s\n", __FUNCTION__);

Drop both printks? Are they useful?
> +}
>
> +static void enable_dev(struct device *dev)
> +{
>    dev->ops->init = init;
>
> +}
>
> +struct chip_operations mainboard_pcengines_alix1c_ops = {
> CHIP_NAME("PC ENGINES  ALIX1C Mainboard")

CHIP_NAME("PC Engines ALIX1.C Mainboard")
>    .enable_dev = enable_dev,
>
> +};
> Index: src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
>
> --- src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	(revision 0)
> +++ src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	(revision 0)

Add a license header, please.
> @@ -0,0 +1,118 @@
> +#define ASSEMBLY 1
>
> +#include <stdint.h>
> +#include <device/pci_def.h>
> +#include <arch/io.h>
> +#include <device/pnp_def.h>
> +#include <arch/romcc_io.h>
> +#include <arch/hlt.h>
> +#include "pc80/serial.c"
> +#include "arch/i386/lib/console.c"
> +#include "ram/ramtest.c"
> +#include "cpu/x86/bist.h"
> +#include "cpu/x86/msr.h"
> +#include <cpu/amd/lxdef.h>
> +#include <cpu/amd/geode_post_code.h>
> +#include "southbridge/amd/cs5536/cs5536.h"
>
> +#define POST_CODE(x) outb(x, 0x80)

We have a global implementation already.
> +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
>
> +#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
> +#include "southbridge/amd/cs5536/cs5536_early_setup.c"
> +#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
>
> +static inline int spd_read_byte(unsigned device, unsigned address)
> +{
> return smbus_read_byte(device, address);
>
> +}
>
> +#define ManualConf 0		/* Do automatic strapped PLL config */
> +#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
> +#define PLLMSRlo 0x02000030
> +#define DIMM0 0xA0
> +#define DIMM1 0xA2
> +#include "northbridge/amd/lx/raminit.h"
> +#include "northbridge/amd/lx/pll_reset.c"
> +#include "northbridge/amd/lx/raminit.c"
> +#include "sdram/generic_sdram.c"
> +#include "cpu/amd/model_lx/cpureginit.c"
> +#include "cpu/amd/model_lx/syspreinit.c"
>
> +static void msr_init(void)
> +{
> msr_t msr;
> /* Setup access to the MC for under 1MB. Note MC not setup yet. */
> msr.hi = 0x24fffc02;
> msr.lo =  0x10010000;
> wrmsr(CPU_RCONF_DEFAULT, msr);
> msr.hi = 0x20000000;
> msr.lo = 0xfff00;
> wrmsr(MSR_GLIU0 + 0x20, msr);
> msr.hi = 0x20000000;
> msr.lo =  0xfff00;
> wrmsr(MSR_GLIU1 + 0x20, msr);
>
> +}

Is this board-specific or chipset-specific? If the latter, it should not
be here.
> +static void mb_gpio_init(void)
> +{
> /* Early mainboard specific GPIO setup */
>
> +}
>
> +void cache_as_ram_main(void)
> +{
> extern void RestartCAR();
> POST_CODE(0x01);
> static const struct mem_controller memctrl [] = {
> {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
> };
> SystemPreInit();
> msr_init();
> cs5536_early_setup();
> /* NOTE: must do this AFTER the early_setup!
> * it is counting on some early MSR setup
> * for cs5536
> */
> cs5536_disable_internal_uart();
> w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
> mb_gpio_init();
> uart_init();
> console_init();
> pll_reset(ManualConf);
> cpuRegInit();
> sdram_initialize(1, memctrl);
> /* Check all of memory */

Only checks _some_ memory.
> ram_check(0x00000000, 640*1024);
> /* Switch from Cache as RAM to real RAM */
> /* There are two ways we could think about this.
> 1. If we are using the auto.inc ROMCC way, the stack is going to be re-setup in the code following this code.
> Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
> 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
> That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
> as the rest of LinuxBIOS. If that is the case we can just do a wbinvd. The stack will be written into real
> RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
> where LB would like it, you need to write some code to do a copy from cache to RAM
> We use method 1 on Norwich and on this board too. 
> */

This comment is in some other file, too. Maybe it should go in the wiki
or in the generic CAR code somewhere? No need to duplicate it in every
LX board...
> POST_CODE(0x02);
> print_err("POST 02\n");
> __asm__("wbinvd\n");

Don't we have a wbinvd() function? Or is that in v3 only?
> print_err("Past wbinvd\n");
> /* we are finding the return does not work on this board. Explicitly call the label that is
> * after the call to us. This is gross, but sometimes at this level it is the only way out
> */
> done_cache_as_ram_main();
>
> +}
> Index: targets/pcengines/alix1c/Config.lb
> ===================================================================
> --- targets/pcengines/alix1c/Config.lb	(revision 0)
> +++ targets/pcengines/alix1c/Config.lb	(revision 0)

Add a license header, please.
> @@ -0,0 +1,26 @@
> +target alix1c
> +mainboard pcengines/alix1c
>
> +option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
>
> +## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
> +## (normal AND fallback images and payloads).
> +## leave 36k for vsa 
> +##
> +option ROM_SIZE = 512*1024 - 36 * 1024
>
> +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
> +## not including any payload.
> +option ROM_IMAGE_SIZE=64*1024
>
> +option FALLBACK_SIZE = ROM_SIZE
>
> +option DEFAULT_CONSOLE_LOGLEVEL = 11
> +option MAXIMUM_CONSOLE_LOGLEVEL = 11

Is 11 valid? Isn't 9 the maximum? Anyway, I guess this can be dropped
and the defaults in Options.lb set to 11 then? Yeah, just a minor issue.
> +romimage "fallback"
> option USE_FALLBACK_IMAGE=1
> option LINUXBIOS_EXTRA_VERSION=".0Fallback"
> payload /tmp/filo.elf
>
> +end
>
> +buildrom ./linuxbios.rom ROM_SIZE  "fallback"

HTH, Uwe.