[coreboot] r3594 - in trunk/coreboot-v2/src: mainboard/asus/a8n_e superio/ite/it8712f

Author: mjones
Date: 2008-09-24 00:19:27 +0200 (Wed, 24 Sep 2008)
New Revision: 3594

Modified:
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
   trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c
Log:
The AMD dbm690t mainboard uses the it8712f SIO with the
default 48MHz clock input. The Asus a8n_e uses the it8712f
with a 24MHz clock input. The it8712f early init code was
setting a 24MHz input clock(to support the a8n_e).
Since 48Mhz is the default I added a function to set 24MHz
input clock to the a8n_e.

Signed-off-by: Marc Jones 
Acked-by: Rudolf Marek

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c	2008-09-23 21:57:33 UTC (rev 3593)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c	2008-09-23 22:19:27 UTC (rev 3594)
@@ -221,6 +221,7 @@
    	bsp_apicid = init_cpus(cpu_init_detectedx);
    }

+	it8712f_24mhz_clkin();
    it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
    uart_init();
    console_init();

Modified: trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c	2008-09-23 21:57:33 UTC (rev 3593)
+++ trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c	2008-09-23 22:19:27 UTC (rev 3594)
@@ -45,10 +45,10 @@
    outb(value, SIO_DATA);
 }

-/* Enable the peripheral devices on the IT8712F Super I/O chip. */
-static void it8712f_enable_serial(device_t dev, unsigned iobase)
+
+static void it8712f_enter_conf(void)
 {
-	/* (1) Enter the configuration state (MB PnP mode). */
+	/*  Enter the configuration state (MB PnP mode). */

/* Perform MB PnP setup to put the SIO chip at 0x2e. */
    /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
@@ -57,7 +57,33 @@
    outb(0x01, IT8712F_CONFIGURATION_PORT);
    outb(0x55, IT8712F_CONFIGURATION_PORT);
    outb(0x55, IT8712F_CONFIGURATION_PORT);
+}

+static void it8712f_exit_conf(void)
+{
+	/* Exit the configuration state (MB PnP mode). */
+	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+}
+
+
+static void it8712f_24mhz_clkin(void)
+{
+	it8712f_enter_conf();
+
+	/* Select 24MHz CLKIN (48MHZ default)*/
+	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
+
+	it8712f_exit_conf();
+
+}
+
+/* Enable the peripheral devices on the IT8712F Super I/O chip. */
+static void it8712f_enable_serial(device_t dev, unsigned iobase)
+{
+
+	/* (1) Enter the configuration state (MB PnP mode). */
+	it8712f_enter_conf();
+
    /* (2) Modify the data of configuration registers. */

/* Select the chip to configure (if there's more than one).
@@ -69,13 +95,9 @@
    it8712f_sio_write(IT8712F_SP1,  0x30, 0x1); /* Serial port 1 */
    it8712f_sio_write(IT8712F_SP2,  0x30, 0x1); /* Serial port 2 */

-	/* Select 24MHz CLKIN (set bit 0). */
-	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01);
-
    /* Clear software suspend mode (clear bit 0). TODO: Needed? */
    /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */

/* (3) Exit the configuration state (MB PnP mode). */
-	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+	it8712f_exit_conf();
 }
-