Scott Duplichan wrote:
]the bootblock doesn't correctly set up ROM mapping correctly.
That is a good point about rom mapping. According to the 8111 document, only the top 64KB is decoded by default. Simnow confirms this, and won't boot the DL145 G1coreboot image.
Good find.
If I manually issue these PCI config writes while execution is still in the top 64KB, the entire 512KB is decoded and simnow will boot the coreboot image:
// write to AMD 8131 Link Command Register BUID field (bits 16-20) // with value 2 so that the 8111 can be accessed: -epcid 0 0 0 c0 00420008 // bus 0, dev 0, fun 0, reg 0xc0
Is it safe to blindly write this word in src/northbridge/amd/amdfam10/bootblock.c ? I think this is what is missing.
// write to AMD 8111 Rom Decode Control Register and set bit 7 // to enable LPC memory decoding of the top 4MB of 4GB space: -epcib 0 1 0 43 80 // bus 0, dev 1, fun 0, reg 0x43
This is already done in src/southbridge/amd/amd8111/bootblock.c for device id 1022:7468 - is this the correct device for that board?
amd8111/Kconfig has
config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC select TINY_BOOTBLOCK
..and always pulls in bootblock.c. The function should get called. But I think the northbridge config that Scott points to may be missing.
//Peter