This was indeed the problem. I have a soc with B0 stepping, so I needed to load a different microcode than the one referred to in the code, but other than that it works fine. I’m getting a lot of output, and it seems it goes through the different FSP stages without a hitch.
Just for my own understanding; is it common for microcode loading to be required as part of the booting process, as opposed to being optional updates?
Thanks a lot for the help everyone,
Gerald
On 04 Jun 2014, at 00:17, Paul Menzel paulepanter@users.sourceforge.net wrote:
Dear Gerald,
Am Dienstag, den 03.06.2014, 14:03 +0200 schrieb Gerald Otter:
I am trying to run coreboot + seabios payload on the bayley bay crb with the recently committed FSP integration, but have had no luck so far. This crb uses the bay trail I (now atom e3800) soc from intel.
Following the instructions from commit d75800c7f , I have built a 2MB image and flashed it to the upper 2MB of the 8MB flash, leaving the TXE / flash descriptor intact. I have added the config from the build. The FSP I used is BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014, together with the flash descriptor and TXE from the 80.21 bios provided by intel, and vga bios 36.2.2. Fwiw, I have tried both the 32bit and 64bit releases of the bios, even though the flash descriptor and TXE binary seem to be exactly the same.
The issue I’m running into is that I have no idea if anything is running at all. There is no output on the VGA/HDMI ports or uart.
The legacy uart referred to in the source is working correctly with the original intel bios, but does not produce any output with the coreboot image. I have tried the most common baud rates (115200, 19200, 9600 ) and did some measurements with a scope in case I got the baud rate wrong, but no cigar. The uart I’m using is the PCU uart, as opposed to hsuart1/2 and the superIO uart. This matches with the configuration in coreboot when compared to the datasheet, so I’m assuming I got this set up correctly. Unfortunately, this is about all the information I have, so I hope I am missing something obvious when building the image / flashing it, etc.
[…]
it looks like you are missing the microcode. (Next time please also send the output of `build/cbfstool build/coreboot.rom print`.)
Could you please test if selecting “Generate from tree” in the prompt “Include CPU microcode in CBFS”?
In the `.config`, instead of
# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set CONFIG_CPU_MICROCODE_CBFS_NONE=yyou should have the one below.
CONFIG_CPU_MICROCODE_CBFS_GENERATE=y # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set # CONFIG_CPU_MICROCODE_CBFS_NONE is not setThanks,
Paul
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