On Sun, Oct 05, 2008 at 01:27:01AM +0200, Vincent Legoll wrote:
I'm trying to understand i855pm code, and reading reset_test.c, I see: #define MCH_DRC 0x70
whereas the 252613.pdf I downloaded from intel web site, at: http://www.intel.com/Assets/PDF/datasheet/252613.pdf "Intel(R) 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet" revision 003, page 71, has the following:
3.7.20. DRC – DRAM Controller Mode Register – Device #0 Offset: 7C-7Fh Default: 1000_0001h Access: Read/Write Size: 32 bits
So what am I missing in the 0x70h versus 0x7Ch difference ?
Could someone please gently enlighten me ?
Looks like a typo to me, I guess in the code, but it could also be in the datasheet.
Be careful with the 855pm code though, I think it's unfinished and possibly never ever worked. If you really plan to add support for some newer Intel chipsets (which is not a small project mind you), I'd start with the i3100 code, which is in good shape quality-wise and has been confirmed working on hardware.
Uwe.