See patch.
I also cleaned up the Debug Port page in the wiki a bit.
http://www.coreboot.org/EHCI_Debug_Port
For now I marked all chipsets where we have Debug Port code as untested, I have a feeling the functionality was rarely tested recently (or at all) so we should only mark those chipsets as tested where we actually have recent test reports.
I'm not sure about the SiS966 Debug Port code, it looks copy-pasted from MCP55 to me, not sure if the functionality actually exists on that chipset and if the code is correct for that. Maybe someone with a SiS966 board could test this?
I'll be able to test on two more chipsets (MCP55, ICH7) and mark them as tested in the wiki then, will report back. Can somebody test SB700? I guess it works fine as the SB600 does too, but a test report would be nice.
Uwe.