[coreboot] r595 - in coreboot-v3: device southbridge/amd/cs5536

Author: hailfinger
Date: 2008-02-13 23:47:58 +0100 (Wed, 13 Feb 2008)
New Revision: 595

Modified:
   coreboot-v3/device/Kconfig
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
Log:
Enable Suspend-to-RAM code based on config option. Revert semantics to
those we had in v2 and before r385.
This causes pm_chipset_init() to be called on Geode LX.

Signed-off-by: Carl-Daniel Hailfinger

Builds and run to filo.
Acked-by: Marc Jones

Modified: coreboot-v3/device/Kconfig
===================================================================
--- coreboot-v3/device/Kconfig	2008-02-13 22:15:59 UTC (rev 594)
+++ coreboot-v3/device/Kconfig	2008-02-13 22:47:58 UTC (rev 595)
@@ -87,3 +87,13 @@

endmenu

+menu "Power management"
+
+config SUSPEND_TO_RAM
+	bool "Suspend-to-RAM (S3)"
+	depends EXPERIMENTAL && BROKEN
+	help
+	  Enable support for Suspend-to-RAM (S3) functionality.
+
+endmenu
+

Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-02-13 22:15:59 UTC (rev 594)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-02-13 22:47:58 UTC (rev 595)
@@ -488,8 +488,9 @@
    }
    sb = (struct southbridge_amd_cs5536_dts_config *)dev->device_configuration;

-#if 0
+#ifdef CONFIG_SUSPEND_TO_RAM
    if (!IsS3Resume())
+#endif
    {
    	struct acpi_init *aci = acpi_init_table;
    	for (; aci->ioreg; aci++) {
@@ -498,7 +499,6 @@
    	}
    	pm_chipset_init();
    }
-#endif

/* Set HD IRQ. */
    outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);