I tried it with and without the little patch below ( and of course with the "big" patch) and it freezes after 2 seconds:
Memtest86+ v4.00 | Pass 0% AMD K10 (65nm) @ 2000 MHz | Test 3% # L1 Cache: 64K 30303 MB/s | Test #0 [Address test, walking ones] L2 Cache: 512K 10050 MB/s | Testing: 4096M - 6144M 16G L3 Cache: 2048K 5649 MB/s | Pattern: 00000000 Memory : 16G 1122 MB/s |------------------------------------------------- Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off) Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits)
WallTime Cached RsvdMem MemMap Cache ECC Test Pass Errors ECC Errs --------- ------ ------- -------- ----- --- ---- ---- ------ -------- 0:00:02 16G 0K coreboot on off Std 0 0 -----------------------------------------------------------------------------
If you need some more output of whatever just ask me.
bye and thx, Knut Kujat
Stefan Reinauer escribió:
On 1/23/10 5:43 PM, Samuel D. wrote:
I don't have any way to test this patch right now, so I'll just add it in upcoming 4.01.
Thanks for your work.
Sam.
Dear Sam,
there was an additional bug I introduced. On top of the other patch, you need to apply this:
Index: coreboot.c
--- coreboot.c (revision 2775) +++ coreboot.c (working copy) @@ -123,7 +123,8 @@ /* if there is, all valid information is in the * referenced coreboot table */
head = __find_cb_table(forward->forward, 0x1000);
head = __find_cb_table(forward->forward,
forward->forward + 0x1000);
}
return head;
In addition I suggest to add the following patch:
*Index: memsize.c
--- memsize.c (revision 2775) +++ memsize.c (working copy) @@ -125,7 +125,7 @@ n++; } v->msegs = n;
- cprint(LINE_INFO, COL_MMAP, "corebt");
- cprint(LINE_INFO, COL_MMAP, "coreboot");
} static void memsize_820() {*
The other memory table types only output 6 characters here, but the field is 8 characters, so no need to abbreviate. Sorry I didn't notice this earlier.
Best regards, Stefan
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